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A bug of ram.read_dataflow() appeared when the burst length is 1 is fixed.
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43 files changed

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‎examples/axi_matmul/test_axi_matmul.py‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -763,6 +763,7 @@
763763
ram_a_0_addr <= 0;
764764
_tmp_35 <= 15;
765765
_tmp_31 <= 1;
766+
_tmp_33 <= 0;
766767
end
767768
if((_tmp_26 || !_tmp_24) && (_tmp_27 || !_tmp_25) && (_tmp_35 > 0)) begin
768769
ram_a_0_addr <= ram_a_0_addr + 1;
@@ -833,6 +834,7 @@
833834
ram_b_0_addr <= 0;
834835
_tmp_47 <= 15;
835836
_tmp_43 <= 1;
837+
_tmp_45 <= 0;
836838
end
837839
if((_tmp_38 || !_tmp_36) && (_tmp_39 || !_tmp_37) && (_tmp_47 > 0)) begin
838840
ram_b_0_addr <= ram_b_0_addr + 1;
@@ -903,6 +905,7 @@
903905
ram_c_0_addr <= 0;
904906
_tmp_67 <= 15;
905907
_tmp_63 <= 1;
908+
_tmp_65 <= 0;
906909
end
907910
if((_tmp_58 || !_tmp_56) && (_tmp_59 || !_tmp_57) && (_tmp_67 > 0)) begin
908911
ram_c_0_addr <= ram_c_0_addr + 1;

‎examples/axi_vecadd/test_axi_vecadd.py‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -799,6 +799,7 @@
799799
ram_a_0_addr <= 0;
800800
_tmp_35 <= 63;
801801
_tmp_31 <= 1;
802+
_tmp_33 <= 0;
802803
end
803804
if((_tmp_26 || !_tmp_24) && (_tmp_27 || !_tmp_25) && (_tmp_35 > 0)) begin
804805
ram_a_0_addr <= ram_a_0_addr + 1;
@@ -895,6 +896,7 @@
895896
ram_b_0_addr <= 0;
896897
_tmp_47 <= 63;
897898
_tmp_43 <= 1;
899+
_tmp_45 <= 0;
898900
end
899901
if((_tmp_38 || !_tmp_36) && (_tmp_39 || !_tmp_37) && (_tmp_47 > 0)) begin
900902
ram_b_0_addr <= ram_b_0_addr + 1;
@@ -965,6 +967,7 @@
965967
ram_c_0_addr <= 0;
966968
_tmp_65 <= 63;
967969
_tmp_61 <= 1;
970+
_tmp_63 <= 0;
968971
end
969972
if((_tmp_56 || !_tmp_54) && (_tmp_57 || !_tmp_55) && (_tmp_65 > 0)) begin
970973
ram_c_0_addr <= ram_c_0_addr + 1;

‎examples/thread_matmul/test_thread_matmul.py‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -807,6 +807,7 @@
807807
ram_c_0_addr <= _tmp_30;
808808
_tmp_47 <= _tmp_32 - 1;
809809
_tmp_43 <= 1;
810+
_tmp_45 <= _tmp_32 == 1;
810811
end
811812
if((_tmp_38 || !_tmp_36) && (_tmp_39 || !_tmp_37) && (_tmp_47 > 0)) begin
812813
ram_c_0_addr <= ram_c_0_addr + 1;

‎examples/thread_matmul_ipcore/test_thread_matmul_ipcore.py‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1413,6 +1413,7 @@
14131413
ram_c_0_addr <= _tmp_39;
14141414
_tmp_56 <= _tmp_41 - 1;
14151415
_tmp_52 <= 1;
1416+
_tmp_54 <= _tmp_41 == 1;
14161417
end
14171418
if((_tmp_47 || !_tmp_45) && (_tmp_48 || !_tmp_46) && (_tmp_56 > 0)) begin
14181419
ram_c_0_addr <= ram_c_0_addr + 1;

‎examples/thread_stream_matmul/test_thread_stream_matmul.py‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -747,6 +747,7 @@
747747
ram_a_0_addr <= 0;
748748
_tmp_37 <= _th_matmul_matrix_size_5 - 1;
749749
_tmp_33 <= 1;
750+
_tmp_35 <= _th_matmul_matrix_size_5 == 1;
750751
end
751752
if((_tmp_28 || !_tmp_26) && (_tmp_29 || !_tmp_27) && (_tmp_37 > 0)) begin
752753
ram_a_0_addr <= ram_a_0_addr + 1;
@@ -817,6 +818,7 @@
817818
ram_b_0_addr <= 0;
818819
_tmp_49 <= _th_matmul_matrix_size_5 - 1;
819820
_tmp_45 <= 1;
821+
_tmp_47 <= _th_matmul_matrix_size_5 == 1;
820822
end
821823
if((_tmp_40 || !_tmp_38) && (_tmp_41 || !_tmp_39) && (_tmp_49 > 0)) begin
822824
ram_b_0_addr <= ram_b_0_addr + 1;
@@ -905,6 +907,7 @@
905907
ram_c_0_addr <= _tmp_55;
906908
_tmp_72 <= _tmp_57 - 1;
907909
_tmp_68 <= 1;
910+
_tmp_70 <= _tmp_57 == 1;
908911
end
909912
if((_tmp_63 || !_tmp_61) && (_tmp_64 || !_tmp_62) && (_tmp_72 > 0)) begin
910913
ram_c_0_addr <= ram_c_0_addr + 1;

‎tests/extension/thread_/axi_dma/test_thread_axi_dma.py‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -836,6 +836,7 @@
836836
myram_0_addr <= _tmp_1;
837837
_tmp_18 <= _tmp_3 - 1;
838838
_tmp_14 <= 1;
839+
_tmp_16 <= _tmp_3 == 1;
839840
end
840841
if((_tmp_9 || !_tmp_7) && (_tmp_10 || !_tmp_8) && (_tmp_18 > 0)) begin
841842
myram_0_addr <= myram_0_addr + 1;
@@ -872,6 +873,7 @@
872873
myram_0_addr <= _tmp_23;
873874
_tmp_40 <= _tmp_25 - 1;
874875
_tmp_36 <= 1;
876+
_tmp_38 <= _tmp_25 == 1;
875877
end
876878
if((_tmp_31 || !_tmp_29) && (_tmp_32 || !_tmp_30) && (_tmp_40 > 0)) begin
877879
myram_0_addr <= myram_0_addr + 1;

‎tests/extension/thread_/axi_dma_async/test_thread_axi_dma_async.py‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -908,6 +908,7 @@
908908
myram_1_addr <= _tmp_1;
909909
_tmp_18 <= _tmp_3 - 1;
910910
_tmp_14 <= 1;
911+
_tmp_16 <= _tmp_3 == 1;
911912
end
912913
if((_tmp_9 || !_tmp_7) && (_tmp_10 || !_tmp_8) && (_tmp_18 > 0)) begin
913914
myram_1_addr <= myram_1_addr + 1;
@@ -944,6 +945,7 @@
944945
myram_1_addr <= _tmp_23;
945946
_tmp_40 <= _tmp_25 - 1;
946947
_tmp_36 <= 1;
948+
_tmp_38 <= _tmp_25 == 1;
947949
end
948950
if((_tmp_31 || !_tmp_29) && (_tmp_32 || !_tmp_30) && (_tmp_40 > 0)) begin
949951
myram_1_addr <= myram_1_addr + 1;

‎tests/extension/thread_/axi_dma_long/test_thread_axi_dma_long.py‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -835,6 +835,7 @@
835835
myram_0_addr <= _tmp_1;
836836
_tmp_18 <= _tmp_3 - 1;
837837
_tmp_14 <= 1;
838+
_tmp_16 <= _tmp_3 == 1;
838839
end
839840
if((_tmp_9 || !_tmp_7) && (_tmp_10 || !_tmp_8) && (_tmp_18 > 0)) begin
840841
myram_0_addr <= myram_0_addr + 1;
@@ -871,6 +872,7 @@
871872
myram_0_addr <= _tmp_23;
872873
_tmp_40 <= _tmp_25 - 1;
873874
_tmp_36 <= 1;
875+
_tmp_38 <= _tmp_25 == 1;
874876
end
875877
if((_tmp_31 || !_tmp_29) && (_tmp_32 || !_tmp_30) && (_tmp_40 > 0)) begin
876878
myram_0_addr <= myram_0_addr + 1;

‎tests/extension/thread_/axi_dma_long_narrow/test_thread_axi_dma_long_narrow.py‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -859,6 +859,7 @@
859859
myram_0_addr <= _tmp_1;
860860
_tmp_18 <= _tmp_3 - 1;
861861
_tmp_14 <= 1;
862+
_tmp_16 <= _tmp_3 == 1;
862863
end
863864
if((_tmp_9 || !_tmp_7) && (_tmp_10 || !_tmp_8) && (_tmp_18 > 0)) begin
864865
myram_0_addr <= myram_0_addr + 1;
@@ -895,6 +896,7 @@
895896
myram_0_addr <= _tmp_28;
896897
_tmp_45 <= _tmp_30 - 1;
897898
_tmp_41 <= 1;
899+
_tmp_43 <= _tmp_30 == 1;
898900
end
899901
if((_tmp_36 || !_tmp_34) && (_tmp_37 || !_tmp_35) && (_tmp_45 > 0)) begin
900902
myram_0_addr <= myram_0_addr + 1;

‎tests/extension/thread_/axi_dma_long_wide/test_thread_axi_dma_long_wide.py‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -949,6 +949,7 @@
949949
myram_0_addr <= _tmp_1;
950950
_tmp_18 <= _tmp_3 - 1;
951951
_tmp_14 <= 1;
952+
_tmp_16 <= _tmp_3 == 1;
952953
end
953954
if((_tmp_9 || !_tmp_7) && (_tmp_10 || !_tmp_8) && (_tmp_18 > 0)) begin
954955
myram_0_addr <= myram_0_addr + 1;
@@ -985,6 +986,7 @@
985986
myram_0_addr <= _tmp_28;
986987
_tmp_45 <= _tmp_30 - 1;
987988
_tmp_41 <= 1;
989+
_tmp_43 <= _tmp_30 == 1;
988990
end
989991
if((_tmp_36 || !_tmp_34) && (_tmp_37 || !_tmp_35) && (_tmp_45 > 0)) begin
990992
myram_0_addr <= myram_0_addr + 1;

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