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1 parent 3560b21 commit 36e7884Copy full SHA for 36e7884
veriloggen/stream/stypes.py
@@ -2174,7 +2174,7 @@ def SraRound(left, right):
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if isinstance(right, int):
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rounder = Sll(Int(1), right - 1)
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else:
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- right_slice = right[0:int(log(right.width, 2))]
+ right_slice = right[0:int(log(left.width, 2))]
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right_slice.latency = 0
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right_slice = right_slice - 1
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