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fix calculation of slice width for SraRound rvalue slice
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veriloggen/stream/stypes.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2174,7 +2174,7 @@ def SraRound(left, right):
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if isinstance(right, int):
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rounder = Sll(Int(1), right - 1)
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else:
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right_slice = right[0:int(log(right.width, 2))]
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right_slice = right[0:int(log(left.width, 2))]
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right_slice.latency = 0
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right_slice = right_slice - 1
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right_slice.latency = 0

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