AxiMemoryModel supports read_word and write_word methods for narrow bit-width operations.

shtaxxx · shtaxxx · commit 3d590d00a989 · 2018-10-02T16:11:27.000+09:00
diff --git a/tests/extension/thread_/memorymodel_readwrite_narrow/Makefile b/tests/extension/thread_/memorymodel_readwrite_narrow/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
diff --git a/tests/extension/thread_/memorymodel_readwrite_narrow/test_thread_memorymodel_readwrite_narrow.py b/tests/extension/thread_/memorymodel_readwrite_narrow/test_thread_memorymodel_readwrite_narrow.py
@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_memorymodel_readwrite_narrow
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_memorymodel_readwrite_narrow.run(filename=None, simtype=simtype,
+                                                   outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')
diff --git a/tests/extension/thread_/memorymodel_readwrite_narrow/thread_memorymodel_readwrite_narrow.py b/tests/extension/thread_/memorymodel_readwrite_narrow/thread_memorymodel_readwrite_narrow.py
@@ -0,0 +1,207 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+import math
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed(axi_datawidth=32, datawidth=4, addrwidth=10):
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    numbanks = int(math.ceil(axi_datawidth / datawidth))
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, axi_datawidth)
+    myram = vthread.MultibankRAM(m, 'myram', clk, rst, datawidth, addrwidth,
+                                 numbanks=numbanks)
+
+    saxi = vthread.AXISLiteRegister(m, 'saxi', clk, rst, 32)
+
+    all_ok = m.TmpReg(initval=0)
+
+    def blink(size):
+        # wait start
+        saxi.wait_flag(0, value=1, resetvalue=0)
+        # reset done
+        saxi.write(1, 0)
+
+        all_ok.value = True
+
+        for i in range(4):
+            print('# iter %d start' % i)
+            # Test for 4KB boundary check
+            offset = i * 1024 * 16 + (myaxi.boundary_size - 4)
+            body(size, offset)
+            print('# iter %d end' % i)
+
+        if all_ok:
+            print('# verify (local): PASSED')
+        else:
+            print('# verify (local): FAILED')
+
+        # result
+        saxi.write(2, all_ok)
+
+        # done
+        saxi.write_flag(1, 1, resetvalue=0)
+
+    def body(size, offset):
+        # write
+        for i in range(size):
+            wdata = (i + 100) % (2 ** datawidth)
+            myram.write(i, wdata)
+
+        laddr = 0
+        gaddr = offset
+        myaxi.dma_write(myram, laddr, gaddr, size)
+        print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
+
+        # write
+        for i in range(size):
+            wdata = (i + 1000) % (2 ** datawidth)
+            myram.write(i, wdata)
+
+        laddr = 0
+        gaddr = (size + size) * 4 + offset
+        myaxi.dma_write(myram, laddr, gaddr, size)
+        print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
+
+        # read
+        laddr = 0
+        gaddr = offset
+        myaxi.dma_read(myram, laddr, gaddr, size)
+        print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
+
+        for i in range(size):
+            rdata = myram.read(i) & (2 ** datawidth - 1)
+            verify = (i + 100) % (2 ** datawidth)
+            if vthread.verilog.NotEql(rdata, verify):
+                print('rdata[%d] = %d (!= %d)' % (i, rdata, verify))
+                all_ok.value = False
+
+        # read
+        laddr = 0
+        gaddr = (size + size) * 4 + offset
+        myaxi.dma_read(myram, laddr, gaddr, size)
+        print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
+
+        for i in range(size):
+            rdata = myram.read(i) & (2 ** datawidth - 1)
+            verify = (i + 1000) % (2 ** datawidth)
+            if vthread.verilog.NotEql(rdata, verify):
+                print('rdata[%d] = %d (!= %d)' % (i, rdata, verify))
+                all_ok.value = False
+
+    th = vthread.Thread(m, 'th_blink', clk, rst, blink)
+    fsm = th.start(16)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    axi_datawidth = 32
+    datawidth = 4
+    addrwidth = 10
+
+    # target instance
+    led = mkLed(axi_datawidth, datawidth, addrwidth)
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    # AXI-Slave controller
+    _saxi = vthread.AXIMLite(m, '_saxi', clk, rst, noio=True)
+    _saxi.connect(ports, 'saxi')
+
+    def ctrl():
+        for i in range(100):
+            pass
+
+        for i in range(16):
+            # word addressing
+            v = memory.read_word(i, 0, datawidth)
+            print('read:  mem[%d] -> %x' % (i, v))
+            v = v + 1024
+            # word addressing
+            memory.write_word(i, 0, datawidth)
+            print('write: mem[%d] <- %x' % (i, v))
+
+        awaddr = 0
+        _saxi.write(awaddr, 1)
+
+        araddr = 4
+        v = _saxi.read(araddr)
+        while v == 0:
+            v = _saxi.read(araddr)
+
+        araddr = 8
+        v = _saxi.read(araddr)
+        if v:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    th = vthread.Thread(m, 'th_ctrl', clk, rst, ctrl)
+    fsm = th.start()
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    # simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)
diff --git a/veriloggen/types/axi.py b/veriloggen/types/axi.py
@@ -1364,7 +1364,8 @@ def AxiLiteSlave(m, name, clk, rst, datawidth=32, addrwidth=32,
 
 
 class AxiMemoryModel(object):
-    __intrinsics__ = ('read', 'write')
+    __intrinsics__ = ('read', 'write',
+                      'read_word', 'write_word')
 
     burst_size_width = 8
 
@@ -1661,6 +1662,60 @@ def write(self, fsm, addr, wdata):
 
         return 0
 
+    def read_word(self, fsm, word_index, byte_offset, bits=8):
+        """ intrinsic method word-indexed read """
+
+        cond = fsm.state == fsm.current
+        rdata = self.m.TmpReg(bits, initval=0, signed=True)
+        num_bytes = int(math.ceil(bits / 8))
+        addr = byte_offset + word_index * bits / 8
+        shift = word_index * bits % 8
+
+        raw_data = vtypes.Cat(*reversed([self.mem[addr + i]
+                                         for i in range(num_bytes)]))
+
+        fsm.If(cond)(
+            rdata(raw_data >> shift)
+        )
+        fsm.goto_next()
+
+        return rdata
+
+    def write_word(self, fsm, word_index, byte_offset, wdata, bits=8):
+        """ intrinsic method word-indexed write """
+
+        cond = fsm.state == fsm.current
+        rdata = self.m.TmpReg(bits, initval=0, signed=True)
+        num_bytes = int(math.ceil(bits / 8))
+        addr = byte_offset + word_index * bits / 8
+        shift = word_index * bits % 8
+
+        wdata_wire = self.m.TmpWire(bits)
+        wdata_wire.assign(wdata)
+        mem_data = vtypes.Cat(*reversed([self.mem[addr + i]
+                                         for i in range(num_bytes)]))
+        mem_data_wire = self.m.TmpWire(8 * num_bytes)
+        mem_data_wire.assign(mem_data)
+
+        inv_mask = self.m.TmpWire(8 * num_bytes)
+        inv_mask.assign(vtypes.Repeat(vtypes.Int(1, 1), bits) << shift)
+        mask = self.m.TmpWire(8 * num_bytes)
+        mask.assign(vtypes.Unot(inv_mask))
+
+        raw_data = vtypes.Or(wdata_wire << shift,
+                             vtypes.Or(mem_data_wire, mask))
+        raw_data_wire = self.m.TmpWire(8 * num_bytes)
+        raw_data_wire.assign(raw_data)
+
+        for i in range(num_bytes):
+            self.fsm.seq.If(cond)(
+                self.mem[addr + i](raw_data_wire[i * 8:i * 8 + 8])
+            )
+
+        fsm.goto_next()
+
+        return 0
+
 
 def make_memory_image(filename, length, pattern='inc', dtype=None,
                       datawidth=32, wordwidth=8, endian='little'):
