Updated examples_obsolete for the parallel pytest with xdist.

Author: shtaxxx

examples_obsolete/Makefile

@@ -14,5 +14,5 @@ run:
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd
 	find . -maxdepth 1 -type d | grep "./" | xargs -I {} make clean -C {}

examples_obsolete/dataflow_example/Makefile

@@ -26,4 +26,4 @@ check:
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

examples_obsolete/dataflow_example/dataflow_example.py

@@ -62,7 +62,8 @@ def mkTest(numports=8):
     reset_stmt.append( yvalid(0) )
     reset_stmt.append( zready(0) )
 
-    simulation.setup_waveform(m, uut)
+    vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    simulation.setup_waveform(m, uut, dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, reset_stmt, period=100)
 

examples_obsolete/dataflow_example/test_dataflow_example.py

@@ -41,7 +41,7 @@
   reg reset_done;
 
   initial begin
-    $dumpfile("uut.vcd");
+    $dumpfile("dataflow_example.vcd");
     $dumpvars(0, uut);
   end
 

examples_obsolete/dataflow_fft4/Makefile

@@ -26,4 +26,4 @@ check:
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

examples_obsolete/dataflow_fft4/dataflow_fft4.py

@@ -10,21 +10,25 @@
 import veriloggen.dataflow as dataflow
 import veriloggen.types.fixed as fixed
 
-#-------------------------------------------------------------------------------
+# -------------------------------------------------------------------------------
+
+
 def complex_add(x, y):
     a = x[0]
     b = x[1]
     c = y[0]
     d = y[1]
     return (a + c), (b + d)
 
+
 def complex_sub(x, y):
     a = x[0]
     b = x[1]
     c = y[0]
     d = y[1]
     return (a - c), (b - d)
 
+
 def complex_mult(x, y):
     a = x[0]
     b = x[1]
@@ -39,22 +43,25 @@ def complex_mult(x, y):
     im = ad + bc
     return re, im
 
+
 def radix2(x, y, c):
     d0 = complex_add(x, y)
     d1 = complex_sub(x, y)
-    r0 = d0 # as-is
+    r0 = d0  # as-is
     r1 = complex_mult(d1, c)
     return r0, r1
 
-#-------------------------------------------------------------------------------
+# -------------------------------------------------------------------------------
+
+
 def fft4(din):
-    w = [ (1, 0), (0, -1), (1, 0), (1, 0) ]
+    w = [(1, 0), (0, -1), (1, 0), (1, 0)]
     a, b = radix2(din[0], din[2], w[0])
     c, d = radix2(din[1], din[3], w[1])
-    
+
     rslt = []
-    rslt.extend( radix2(a, c, w[2]) )
-    rslt.extend( radix2(b, d, w[3]) )
+    rslt.extend(radix2(a, c, w[2]))
+    rslt.extend(radix2(b, d, w[3]))
 
     # reorder by bit-inversed index
     ret = []
@@ -64,15 +71,17 @@ def fft4(din):
         index = int(fm.format(i)[::-1], 2)
         #print(i, '->', index)
         re, im = rslt[index]
-        ret.append( (re, im) )
+        ret.append((re, im))
 
     return ret
 
-#-------------------------------------------------------------------------------
+# -------------------------------------------------------------------------------
+
+
 def mkFFT4(datawidth=16, point=8):
-    din = [ (dataflow.Variable('din' + str(i) + 're', width=datawidth, point=point, signed=True),
-             dataflow.Variable('din' + str(i) + 'im', width=datawidth, point=point, signed=True))
-            for i in range(4) ]
+    din = [(dataflow.Variable('din' + str(i) + 're', width=datawidth, point=point, signed=True),
+            dataflow.Variable('din' + str(i) + 'im', width=datawidth, point=point, signed=True))
+           for i in range(4)]
 
     # call software-defined method
     rslt = fft4(din)
@@ -87,60 +96,63 @@ def mkFFT4(datawidth=16, point=8):
     df = dataflow.Dataflow(*vars)
     m = df.to_module('fft4')
 
-    #try:
+    # try:
     #    df.draw_graph()
-    #except:
+    # except:
     #    print('Dataflow graph could not be generated.', file=sys.stderr)
 
     return m
 
-#-------------------------------------------------------------------------------
+# -------------------------------------------------------------------------------
+
+
 def mkTest(datawidth=16, point=8):
     m = Module('test')
 
     main = mkFFT4(datawidth, point)
-    
+
     params = m.copy_params(main)
     ports = m.copy_sim_ports(main)
 
     clk = ports['CLK']
     rst = ports['RST']
 
-    din = [ (ports['din' + str(i) + 're'], ports['din' + str(i) + 'im']) for i in range(4) ]
-    dout = [ (ports['dout' + str(i) + 're'], ports['dout' + str(i) + 'im']) for i in range(4) ]
+    din = [(ports['din' + str(i) + 're'], ports['din' + str(i) + 'im']) for i in range(4)]
+    dout = [(ports['dout' + str(i) + 're'], ports['dout' + str(i) + 'im']) for i in range(4)]
+
+    _din = [(m.WireLike(re, name='_' + re.name, width=datawidth - point),
+             m.WireLike(im, name='_' + im.name, width=datawidth - point))
+            for re, im in din]
+    _dout = [(m.WireLike(re, name='_' + re.name, width=datawidth - point),
+              m.WireLike(im, name='_' + im.name, width=datawidth - point))
+             for re, im in dout]
 
-    _din = [ (m.WireLike(re, name='_' + re.name, width=datawidth-point),
-              m.WireLike(im, name='_' + im.name, width=datawidth-point))
-             for re, im in din ]
-    _dout = [ (m.WireLike(re, name='_' + re.name, width=datawidth-point),
-               m.WireLike(im, name='_' + im.name, width=datawidth-point))
-              for re, im in dout ]
-    
     for (lre, lim), (rre, rim) in zip(_din, din):
-        m.Assign( lre(fixed.fixed_to_int(rre, point)) )
-        m.Assign( lim(fixed.fixed_to_int(rim, point)) )
-    
+        m.Assign(lre(fixed.fixed_to_int(rre, point)))
+        m.Assign(lim(fixed.fixed_to_int(rim, point)))
+
     for (lre, lim), (rre, rim) in zip(_dout, dout):
-        m.Assign( lre(fixed.fixed_to_int(rre, point)) )
-        m.Assign( lim(fixed.fixed_to_int(rim, point)) )
-    
+        m.Assign(lre(fixed.fixed_to_int(rre, point)))
+        m.Assign(lim(fixed.fixed_to_int(rim, point)))
+
     uut = m.Instance(main, 'uut',
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
     reset_done = m.Reg('reset_done', initval=0)
     reset_stmt = []
-    reset_stmt.append( reset_done(0) )
+    reset_stmt.append(reset_done(0))
     for i, (re, im) in enumerate(din):
-        reset_stmt.append( re(fixed.to_fixed(i, point)) )
-        reset_stmt.append( im(fixed.to_fixed(i, point)) )
-    
-    simulation.setup_waveform(m, uut, *(_din + _dout))
+        reset_stmt.append(re(fixed.to_fixed(i, point)))
+        reset_stmt.append(im(fixed.to_fixed(i, point)))
+
+    vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    simulation.setup_waveform(m, uut, *(_din + _dout), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, reset_stmt, period=100)
 
     nclk = simulation.next_clock
-    
+
     init.add(
         Delay(1000),
         reset_done(1),
@@ -151,56 +163,57 @@ def mkTest(datawidth=16, point=8):
 
     def dump(name, v, point):
         return Systask('display', name + '= %f', fixed.fixed_to_real(v, point))
-        
+
     send_fsm = FSM(m, 'send_fsm', clk, rst)
     send_fsm.goto_next(cond=reset_done)
 
     for i, (re, im) in enumerate(din):
-        send_fsm.add( re(fixed.to_fixed(i, point)) )
-        send_fsm.add( im(fixed.to_fixed(i, point)) )
+        send_fsm.add(re(fixed.to_fixed(i, point)))
+        send_fsm.add(im(fixed.to_fixed(i, point)))
     #    send_fsm.add( dump('din[%d]re' % i, re, point), delay=1 )
     #    send_fsm.add( dump('din[%d]im' % i, im, point), delay=1 )
-        
+
     send_fsm.goto_next()
 
     for i, (re, im) in enumerate(din):
-        send_fsm.add( re(fixed.to_fixed(0, point)) )
-        send_fsm.add( im(fixed.to_fixed(0, point)) )
-        
+        send_fsm.add(re(fixed.to_fixed(0, point)))
+        send_fsm.add(im(fixed.to_fixed(0, point)))
+
     send_fsm.goto_next()
 
     for _ in range(100):
-        #for i, (re, im) in enumerate(dout):
+        # for i, (re, im) in enumerate(dout):
         #    send_fsm.add( dump('dout[%d]re' % i, re, point), delay=1 )
         #    send_fsm.add( dump('dout[%d]im' % i, im, point), delay=1 )
-            
+
         send_fsm.goto_next()
 
-    send_fsm.add( Systask('finish') )
+    send_fsm.add(Systask('finish'))
 
     send_fsm.make_always()
 
     return m
 
+
 if __name__ == '__main__':
     n = 4
     point = 8
     test = mkTest(point=point)
     verilog = test.to_verilog('tmp.v')
-    #print(verilog)
+    # print(verilog)
 
     # run simulator (Icarus Verilog)
     sim = simulation.Simulator(test)
     rslt = sim.run()
     print(rslt)
 
-    ## only target RTL
+    # only target RTL
     #main = mkFFT4()
     #verilog = main.to_verilog('tmp.v')
-    #print(verilog)
+    # print(verilog)
 
-    din = [ (0, 0), (1, 1), (2, 2), (3, 3) ]
+    din = [(0, 0), (1, 1), (2, 2), (3, 3)]
     rslt = fft4(din)
     for r in rslt:
-        print( complex(round(r[0] * (2 ** point), 5), round(r[1] * (2 ** point), 5)), ':',
-               complex(round(r[0], 5), round(r[1], 5)) )
+        print(complex(round(r[0] * (2 ** point), 5), round(r[1] * (2 ** point), 5)), ':',
+              complex(round(r[0], 5), round(r[1], 5)))

examples_obsolete/dataflow_fft4/test_dataflow_fft4.py

@@ -87,7 +87,7 @@
   reg reset_done;
 
   initial begin
-    $dumpfile("uut.vcd");
+    $dumpfile("dataflow_fft4.vcd");
     $dumpvars(0, uut, _din0re, _din0im, _din1re, _din1im, _din2re, _din2im, _din3re, _din3im, _dout0re, _dout0im, _dout1re, _dout1im, _dout2re, _dout2im, _dout3re, _dout3im);
   end
 

examples_obsolete/dataflow_fftN/Makefile

@@ -26,4 +26,4 @@ check:
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

examples_obsolete/dataflow_fftN/dataflow_fftN.py

@@ -226,7 +226,8 @@ def mkTest(n=8, datawidth=16, point=8):
         reset_stmt.append(re(fixed.to_fixed(wr, point)))
         reset_stmt.append(im(fixed.to_fixed(wi, point)))
 
-    simulation.setup_waveform(m, uut, *(_din + _dout + _weight))
+    vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    simulation.setup_waveform(m, uut, *(_din + _dout + _weight), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, reset_stmt, period=100)
 

examples_obsolete/dataflow_fftN/test_dataflow_fftN.py

@@ -247,7 +247,7 @@
   reg reset_done;
 
   initial begin
-    $dumpfile("uut.vcd");
+    $dumpfile("dataflow_fftN.vcd");
     $dumpvars(0, uut, _din0re, _din0im, _din1re, _din1im, _din2re, _din2im, _din3re, _din3im, _din4re, _din4im, _din5re, _din5im, _din6re, _din6im, _din7re, _din7im, _dout0re, _dout0im, _dout1re, _dout1im, _dout2re, _dout2im, _dout3re, _dout3im, _dout4re, _dout4im, _dout5re, _dout5im, _dout6re, _dout6im, _dout7re, _dout7im, _weight0re, _weight0im, _weight1re, _weight1im, _weight2re, _weight2im, _weight3re, _weight3im, _weight4re, _weight4im, _weight5re, _weight5im, _weight6re, _weight6im, _weight7re, _weight7im, _weight8re, _weight8im, _weight9re, _weight9im, _weight10re, _weight10im, _weight11re, _weight11im);
   end