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vtypes._Variable class has width_msb, width_lsb, length_msb, and length_lsb for prettified output of to_verilog after read_verilog.
1 parent da51e28 commit 47e7575

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15 files changed

+303
-173
lines changed

15 files changed

+303
-173
lines changed

‎examples/read_verilog_code/test_read_verilog_code.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,11 +10,11 @@
1010
(
1111
input CLK,
1212
input RST,
13-
output reg [((WIDTH-1)+1)-1:0] LED,
13+
output reg [WIDTH-1:0] LED,
1414
input enable,
1515
output busy
1616
);
17-
reg [((32-1)+1)-1:0] count;
17+
reg [32-1:0] count;
1818
always @(posedge CLK) begin
1919
if(RST) begin
2020
count <= 0;

‎tests/read_verilog_/branchpredunit/test_read_verilog_branchpredunit.py‎

Lines changed: 78 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -21,24 +21,24 @@
2121
input CLK,
2222
input RST_X,
2323
input EN,
24-
input [((W_A-1)+1)-1:0] pc,
24+
input [W_A-1:0] pc,
2525
output pred,
26-
input [((W_A-1)+1)-1:0] update_pc,
26+
input [W_A-1:0] update_pc,
2727
input update,
2828
input rslt
2929
);
3030
3131
//Branch History Register
32-
reg [((W_BHR-1)+1)-1:0] bhr;
32+
reg [W_BHR-1:0] bhr;
3333
//Pattern History Table
34-
wire [(1+1)-1:0] read_pht;
35-
wire [(1+1)-1:0] update_read_pht;
36-
wire [(1+1)-1:0] write_pht;
34+
wire [1:0] read_pht;
35+
wire [1:0] update_read_pht;
36+
wire [1:0] write_pht;
3737
38-
reg [((W_BHR-1)+1)-1:0] d_bhr;
38+
reg [W_BHR-1:0] d_bhr;
3939
reg d_update;
4040
reg d_rslt;
41-
reg [((W_A-1)+1)-1:0] d_update_pc;
41+
reg [W_A-1:0] d_update_pc;
4242
4343
pht_mem #(.W_PHT(W_PHT), .N_PHT(N_PHT))
4444
pht_mem(CLK, EN, pht_index(bhr, pc), read_pht,
@@ -68,16 +68,16 @@
6868
end
6969
end
7070
71-
function [((W_PHT-1)+1)-1:0] pht_index;
72-
input [((W_BHR-1)+1)-1:0] bhr;
73-
input [((W_A-1)+1)-1:0] pc;
71+
function [W_PHT-1:0] pht_index;
72+
input [W_BHR-1:0] bhr;
73+
input [W_A-1:0] pc;
7474
begin
7575
pht_index = (bhr << BHR_OFFSET) ^ (pc >> 2);
7676
end
7777
endfunction
7878
79-
function [(1+1)-1:0] pht_update;
80-
input [(1+1)-1:0] current;
79+
function [1:0] pht_update;
80+
input [1:0] current;
8181
input rslt;
8282
begin
8383
if(rslt) begin
@@ -88,8 +88,8 @@
8888
end
8989
endfunction
9090
91-
function [(0+1)-1:0] get_pred;
92-
input [(1+1)-1:0] cnt;
91+
function [0:0] get_pred;
92+
input [1:0] cnt;
9393
begin
9494
get_pred = (cnt >= 2)? 1:0;
9595
end
@@ -104,18 +104,18 @@
104104
(
105105
input CLK,
106106
input EN,
107-
input [((W_PHT-1)+1)-1:0] I_A0,
108-
output [(1+1)-1:0] O_Q0,
109-
input [((W_PHT-1)+1)-1:0] I_A1,
110-
output [(1+1)-1:0] O_Q1,
111-
input [((W_PHT-1)+1)-1:0] I_A2,
112-
input [(1+1)-1:0] I_D2,
107+
input [W_PHT-1:0] I_A0,
108+
output [1:0] O_Q0,
109+
input [W_PHT-1:0] I_A1,
110+
output [1:0] O_Q1,
111+
input [W_PHT-1:0] I_A2,
112+
input [1:0] I_D2,
113113
input I_WE2
114114
);
115115
116-
reg [(1+1)-1:0] mem [0:((N_PHT-1)+1)-1];
117-
reg [((W_PHT-1)+1)-1:0] d_I_A0;
118-
reg [((W_PHT-1)+1)-1:0] d_I_A1;
116+
reg [1:0] mem [0:N_PHT-1];
117+
reg [W_PHT-1:0] d_I_A0;
118+
reg [W_PHT-1:0] d_I_A1;
119119
120120
integer i;
121121
initial begin
@@ -148,38 +148,38 @@
148148
(
149149
input CLK, RST_X,
150150
input EN,
151-
input [((W_A-1)+1)-1:0] pc,
152-
output [((W_A-1)+1)-1:0] pred_target,
151+
input [W_A-1:0] pc,
152+
output [W_A-1:0] pred_target,
153153
output exist,
154154
output read_ras,
155-
input [((W_A-1)+1)-1:0] update_pc,
156-
input [((W_A-1)+1)-1:0] update_target,
155+
input [W_A-1:0] update_pc,
156+
input [W_A-1:0] update_target,
157157
input update_read_ras,
158158
input update,
159159
input rslt
160160
);
161161
162162
localparam W_TAG = W_A - (W_TAB + 2);
163163
164-
reg [((W_A-1)+1)-1:0] d_pc;
165-
reg [((W_A-1)+1)-1:0] d_update_pc;
166-
reg [((W_A-1)+1)-1:0] d_update_target;
164+
reg [W_A-1:0] d_pc;
165+
reg [W_A-1:0] d_update_pc;
166+
reg [W_A-1:0] d_update_target;
167167
reg d_update;
168168
reg d_rslt;
169169
reg d_update_read_ras;
170170
171-
// reg [(0+1)-1:0] last [0:((N_TAB-1)+1)-1]; //LRU
172-
// reg [(0+1)-1:0] d_last;
171+
// reg [0:0] last [0:N_TAB-1]; //LRU
172+
// reg [0:0] d_last;
173173
174-
function [((W_TAB-1)+1)-1:0] btb_index;
175-
input [((W_A-1)+1)-1:0] pc;
174+
function [W_TAB-1:0] btb_index;
175+
input [W_A-1:0] pc;
176176
begin
177177
btb_index = pc >> 2;
178178
end
179179
endfunction
180180
181-
function [((W_TAG-1)+1)-1:0] get_tag;
182-
input [((W_A-1)+1)-1:0] pc;
181+
function [W_TAG-1:0] get_tag;
182+
input [W_A-1:0] pc;
183183
begin
184184
get_tag = pc[W_A-1:(W_A-W_TAG)];
185185
end
@@ -200,13 +200,13 @@
200200
wire read_hit;
201201
wire update_hit;
202202
wire victim;
203-
reg [((W_A-1)+1)-1:0] btb [0:((N_TAB-1)+1)-1];
204-
reg [((W_TAG-1)+1)-1:0] tag [0:((N_TAB-1)+1)-1];
205-
wire [((W_TAG-1)+1)-1:0] read_tag;
206-
wire [((W_A-1)+1)-1:0] read_target;
207-
wire [((W_TAG-1)+1)-1:0] update_tag;
203+
reg [W_A-1:0] btb [0:N_TAB-1];
204+
reg [W_TAG-1:0] tag [0:N_TAB-1];
205+
wire [W_TAG-1:0] read_tag;
206+
wire [W_A-1:0] read_target;
207+
wire [W_TAG-1:0] update_tag;
208208
wire t_read_ras;
209-
reg [(0+1)-1:0] ras [0:((N_TAB-1)+1)-1];
209+
reg [0:0] ras [0:N_TAB-1];
210210
wire btb_we;
211211
assign btb_we = d_rslt && d_update && (update_hit || victim);
212212
btb_mem #(.W_A(W_A), .W_TAB(W_TAB), .N_TAB(N_TAB))
@@ -301,15 +301,15 @@
301301
(
302302
input CLK,
303303
input EN,
304-
input [((W_TAB-1)+1)-1:0] I_A0,
305-
output [((W_A-1)+1)-1:0] O_Q0,
306-
input [((W_TAB-1)+1)-1:0] I_A1,
307-
input [((W_A-1)+1)-1:0] I_D1,
304+
input [W_TAB-1:0] I_A0,
305+
output [W_A-1:0] O_Q0,
306+
input [W_TAB-1:0] I_A1,
307+
input [W_A-1:0] I_D1,
308308
input I_WE1
309309
);
310310
311-
reg [((W_A-1)+1)-1:0] btb [0:((N_TAB-1)+1)-1];
312-
reg [((W_TAB-1)+1)-1:0] d_I_A0;
311+
reg [W_A-1:0] btb [0:N_TAB-1];
312+
reg [W_TAB-1:0] d_I_A0;
313313
314314
integer i;
315315
initial begin
@@ -336,19 +336,19 @@
336336
(
337337
input CLK,
338338
input EN,
339-
input [((W_TAB-1)+1)-1:0] I_A0,
340-
output [((W_TAG-1)+1)-1:0] O_Q0,
341-
input [((W_TAB-1)+1)-1:0] I_A1,
342-
output [((W_TAG-1)+1)-1:0] O_Q1,
343-
input [((W_TAB-1)+1)-1:0] I_A2,
344-
input [((W_TAG-1)+1)-1:0] I_D2,
339+
input [W_TAB-1:0] I_A0,
340+
output [W_TAG-1:0] O_Q0,
341+
input [W_TAB-1:0] I_A1,
342+
output [W_TAG-1:0] O_Q1,
343+
input [W_TAB-1:0] I_A2,
344+
input [W_TAG-1:0] I_D2,
345345
input I_WE2
346346
);
347347
348348
localparam W_TAG = W_A - (W_TAB + 2);
349-
reg [((W_TAG-1)+1)-1:0] tag [0:((N_TAB-1)+1)-1];
350-
reg [((W_TAB-1)+1)-1:0] d_I_A0;
351-
reg [((W_TAB-1)+1)-1:0] d_I_A1;
349+
reg [W_TAG-1:0] tag [0:N_TAB-1];
350+
reg [W_TAB-1:0] d_I_A0;
351+
reg [W_TAB-1:0] d_I_A1;
352352
353353
integer i;
354354
initial begin
@@ -378,15 +378,15 @@
378378
(
379379
input CLK,
380380
input EN,
381-
input [((W_TAB-1)+1)-1:0] I_A0,
382-
output [(0+1)-1:0] O_Q0,
383-
input [((W_TAB-1)+1)-1:0] I_A1,
384-
input [(0+1)-1:0] I_D1,
381+
input [W_TAB-1:0] I_A0,
382+
output [0:0] O_Q0,
383+
input [W_TAB-1:0] I_A1,
384+
input [0:0] I_D1,
385385
input I_WE1
386386
);
387387
388-
reg [(0+1)-1:0] ras [0:((N_TAB-1)+1)-1];
389-
reg [((W_TAB-1)+1)-1:0] d_I_A0;
388+
reg [0:0] ras [0:N_TAB-1];
389+
reg [W_TAB-1:0] d_I_A0;
390390
391391
integer i;
392392
initial begin
@@ -419,17 +419,17 @@
419419
input EN,
420420
input I_PUSH,
421421
input I_POP,
422-
input [((W_A-1)+1)-1:0] I_ADDR,
423-
output reg [((W_A-1)+1)-1:0] O_ADDR,
422+
input [W_A-1:0] I_ADDR,
423+
output reg [W_A-1:0] O_ADDR,
424424
output O_OVERFLOW
425425
);
426426
427-
reg [((W_A-1)+1)-1:0] stack [0:(N_STACK+1)-1];
428-
reg [((W_STACK-1)+1)-1:0] head;
429-
reg [((W_CNT-1)+1)-1:0] over_cnt;
427+
reg [W_A-1:0] stack [0:N_STACK];
428+
reg [W_STACK-1:0] head;
429+
reg [W_CNT-1:0] over_cnt;
430430
431431
assign O_OVERFLOW = (over_cnt > 0);
432-
wire [((W_STACK-1)+1)-1:0] read_ptr;
432+
wire [W_STACK-1:0] read_ptr;
433433
assign read_ptr = (head == 0)? 0 : head -1;
434434
//assign O_ADDR = (head == 0)? 0: stack[read_ptr];
435435
@@ -470,9 +470,9 @@
470470
)
471471
input CLK, RST_X;
472472
input EN;
473-
input [((W_A-1)+1)-1:0] pc;
473+
input [W_A-1:0] pc;
474474
output pred;
475-
input [((W_A-1)+1)-1:0] update_pc;
475+
input [W_A-1:0] update_pc;
476476
input update;
477477
input rslt;
478478
assign pred = 0;
@@ -492,12 +492,12 @@
492492
(
493493
input CLK, RST_X,
494494
input EN,
495-
input [((W_A-1)+1)-1:0] pc,
496-
output [((W_A-1)+1)-1:0] pred_target,
495+
input [W_A-1:0] pc,
496+
output [W_A-1:0] pred_target,
497497
output exist,
498498
output read_ras,
499-
input [((W_A-1)+1)-1:0] update_pc,
500-
input [((W_A-1)+1)-1:0] update_target,
499+
input [W_A-1:0] update_pc,
500+
input [W_A-1:0] update_target,
501501
input update_read_ras,
502502
input update,
503503
input rslt
@@ -521,8 +521,8 @@
521521
input EN,
522522
input I_PUSH,
523523
input I_POP,
524-
input [((W_A-1)+1)-1:0] I_ADDR,
525-
output [((W_A-1)+1)-1:0] O_ADDR,
524+
input [W_A-1:0] I_ADDR,
525+
output [W_A-1:0] O_ADDR,
526526
output O_OVERFLOW
527527
);
528528
assign O_ADDR = 0;

‎tests/read_verilog_/module/test_read_verilog_module.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,9 @@
3131
(
3232
input CLK,
3333
input RST,
34-
output reg [((WIDTH-1)+1)-1:0] LED
34+
output reg [WIDTH-1:0] LED
3535
);
36-
reg [((32-1)+1)-1:0] count;
36+
reg [32-1:0] count;
3737
always @(posedge CLK) begin
3838
if(RST) begin
3939
count <= 0;

‎tests/read_verilog_/module_generate/test_read_verilog_module_generate.py‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -32,10 +32,10 @@
3232
(
3333
input CLK,
3434
input RST,
35-
output reg [(WIDTH-1)+1-1:0] LED
35+
output reg [(WIDTH-1):0] LED
3636
);
3737
38-
reg [(32-1)+1-1:0] count;
38+
reg [(32-1):0] count;
3939
4040
always @(posedge CLK) begin
4141
if(RST) begin
@@ -51,13 +51,13 @@
5151
5252
genvar i;
5353
generate for(i=0; i<NUM_INST; i=i+1) begin: gen_for
54-
reg [(32-1)+1-1:0] gen_count;
54+
reg [(32-1):0] gen_count;
5555
if(i == 0) begin: gen_if_true
5656
always @(posedge CLK) begin
5757
gen_count <= count;
5858
end
5959
end else begin: gen_if_false
60-
reg [(32-1)+1-1:0] gen_if_count;
60+
reg [(32-1):0] gen_if_count;
6161
always @(posedge CLK) begin
6262
gen_count <= gen_for[i-1].gen_count;
6363
gen_if_count <= gen_count;

‎tests/read_verilog_/module_initial/test_read_verilog_module_initial.py‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
1313
reg CLK;
1414
reg RST;
15-
wire [(WIDTH-1)+1-1:0] LED;
15+
wire [(WIDTH-1):0] LED;
1616
1717
blinkled #
1818
(
@@ -52,9 +52,9 @@
5252
(
5353
input CLK,
5454
input RST,
55-
output reg [((WIDTH-1)+1)-1:0] LED
55+
output reg [WIDTH-1:0] LED
5656
);
57-
reg [((32-1)+1)-1:0] count;
57+
reg [32-1:0] count;
5858
always @(posedge CLK) begin
5959
if(RST) begin
6060
count <= 0;

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