add_mux -> add_enable_cond and add_mux. add_cond -> add_disable_cond

shtaxxx · shtaxxx · commit 5d70678a9e60 · 2020-12-20T20:22:03.000+09:00
diff --git a/tests/extension/thread_/stream_counter_stall/thread_stream_counter_stall.py b/tests/extension/thread_/stream_counter_stall/thread_stream_counter_stall.py
@@ -44,7 +44,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size)
diff --git a/tests/extension/thread_/stream_linebuffer2d_2_stall/thread_stream_linebuffer2d_2_stall.py b/tests/extension/thread_/stream_linebuffer2d_2_stall/thread_stream_linebuffer2d_2_stall.py
@@ -64,7 +64,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     # for sequential
     ram_bufs = [vthread.RAM(m, 'ram_buf' + str(i), clk, rst, datawidth, addrwidth)
diff --git a/tests/extension/thread_/stream_linebuffer2d_stall/thread_stream_linebuffer2d_stall.py b/tests/extension/thread_/stream_linebuffer2d_stall/thread_stream_linebuffer2d_stall.py
@@ -58,7 +58,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream(width, height, offset):
         strm.set_source('dummy_src', ram_dummy_src, offset, width * height * 2 * 2)
diff --git a/tests/extension/thread_/stream_linebuffer3d_stall/thread_stream_linebuffer3d_stall.py b/tests/extension/thread_/stream_linebuffer3d_stall/thread_stream_linebuffer3d_stall.py
@@ -61,7 +61,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream(channel, width, height, offset):
         strm.set_source('dummy_src', ram_dummy_src, offset, channel * width * height * 2 * 2)
diff --git a/tests/extension/thread_/stream_multipattern_stall/thread_stream_multipattern_stall.py b/tests/extension/thread_/stream_multipattern_stall/thread_stream_multipattern_stall.py
@@ -53,7 +53,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream():
         strm.set_source_multipattern('a', ram_a, offsets, patterns)
diff --git a/tests/extension/thread_/stream_read_modify_write_stall/thread_stream_read_modify_write_stall.py b/tests/extension/thread_/stream_read_modify_write_stall/thread_stream_read_modify_write_stall.py
@@ -47,7 +47,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream(numbins, size, offset):
         for i in range(numbins):
diff --git a/tests/extension/thread_/stream_read_ram_stall/thread_stream_read_ram_stall.py b/tests/extension/thread_/stream_read_ram_stall/thread_stream_read_ram_stall.py
@@ -43,7 +43,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size)
diff --git a/tests/extension/thread_/stream_reduce_stall/thread_stream_reduce_stall.py b/tests/extension/thread_/stream_reduce_stall/thread_stream_reduce_stall.py
@@ -37,7 +37,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size)
diff --git a/tests/extension/thread_/stream_ringbuffer_stall/thread_stream_ringbuffer_stall.py b/tests/extension/thread_/stream_ringbuffer_stall/thread_stream_ringbuffer_stall.py
@@ -45,7 +45,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size * 2)
diff --git a/tests/extension/thread_/stream_scratchpad_stall/thread_stream_scratchpad_stall.py b/tests/extension/thread_/stream_scratchpad_stall/thread_stream_scratchpad_stall.py
@@ -48,7 +48,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size * 2)
diff --git a/tests/extension/thread_/stream_stall/thread_stream_stall.py b/tests/extension/thread_/stream_stall/thread_stream_stall.py
@@ -38,7 +38,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size)
diff --git a/tests/extension/thread_/stream_substream_stall/thread_stream_substream_stall.py b/tests/extension/thread_/stream_substream_stall/thread_stream_substream_stall.py
@@ -38,7 +38,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(mulstrm.stream_oready, 1, count == 0)
+    util.add_disable_cond(mulstrm.stream_oready, 1, count == 0)
 
     macstrm = vthread.Stream(m, 'mac_stream', clk, rst)
     a = macstrm.source('a')
@@ -54,7 +54,7 @@ def mkLed():
     macstrm.sink(sum, 'sum', when=sum_valid, when_name='sum_valid')
 
     # add a stall condition
-    util.add_cond(macstrm.stream_oready, 1, count == 0)
+    util.add_disable_cond(macstrm.stream_oready, 1, count == 0)
 
     actstrm = vthread.Stream(m, 'act_stream', clk, rst)
     a = actstrm.source('a')
@@ -73,7 +73,7 @@ def mkLed():
     actstrm.sink(sum, 'sum', when=sum_valid, when_name='sum_valid')
 
     # add a stall condition
-    util.add_cond(actstrm.stream_oready, 1, count == 0)
+    util.add_disable_cond(actstrm.stream_oready, 1, count == 0)
 
     all_ok = m.TmpReg(initval=0)
 
diff --git a/tests/extension/thread_/stream_write_ram_stall/thread_stream_write_ram_stall.py b/tests/extension/thread_/stream_write_ram_stall/thread_stream_write_ram_stall.py
@@ -51,7 +51,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.stream_oready, 1, count == 0)
 
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size * 2)
diff --git a/veriloggen/thread/axim.py b/veriloggen/thread/axim.py
@@ -990,7 +990,7 @@ def _synthesize_write_fsm_same(self, ram, port, ram_method, ram_datawidth):
             fsm.set_index(3)
             cond = vtypes.Ands(fsm.here, self.write_op_sel == op_id)
             done_out = self.write_dataflow(data, counter, cond=cond)
-            util.add_mux(self.write_data_done, done_out, 1)
+            util.add_enable_cond(self.write_data_done, done_out, 1)
 
             return
 
@@ -1044,7 +1044,7 @@ def _synthesize_write_fsm_same(self, ram, port, ram_method, ram_datawidth):
         # state 3
         cond = vtypes.Ands(fsm.here, self.write_op_sel == op_id)
         done_out = self.write_dataflow(data, counter, cond=cond)
-        util.add_mux(self.write_data_done, done_out, 1)
+        util.add_enable_cond(self.write_data_done, done_out, 1)
 
         fsm.If(self.write_data_done)(
             cur_global_addr.add(optimize(cur_size * (self.datawidth // 8)))
@@ -1599,4 +1599,3 @@ def set_global_base_addr(self, fsm, addr):
         self.seq.If(flag)(
             self.global_base_addr(addr)
         )
-
diff --git a/veriloggen/thread/fifo.py b/veriloggen/thread/fifo.py
@@ -88,7 +88,7 @@ def enq_rtl(self, wdata, cond=None):
             enable = vtypes.Int(1, 1)
 
         util.add_mux(self.wif.wdata, enable, wdata)
-        util.add_mux(self.wif.enq, enable, enq_cond)
+        util.add_enable_cond(self.wif.enq, enable, enq_cond)
 
         ack = self.seq.Prev(ready, 1)
 
@@ -108,7 +108,7 @@ def deq_rtl(self, cond=None):
         else:
             deq_cond = ready
 
-        util.add_mux(self.rif.deq, deq_cond, 1)
+        util.add_enable_cond(self.rif.deq, deq_cond, 1)
 
         data = self.rif.rdata
         valid = self.seq.Prev(deq_cond, 1)
diff --git a/veriloggen/thread/ram.py b/veriloggen/thread/ram.py
@@ -128,7 +128,7 @@ def read_rtl(self, addr, port=0, cond=None):
             enable = vtypes.Int(1, 1)
 
         util.add_mux(self.interfaces[port].addr, enable, addr)
-        util.add_mux(self.interfaces[port].enable, enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].enable, enable, vtypes.Int(1, 1))
 
         rdata = self.interfaces[port].rdata
         rvalid = self.seq.Prev(enable, 1)
@@ -151,8 +151,8 @@ def write_rtl(self, addr, wdata, port=0, cond=None):
 
         util.add_mux(self.interfaces[port].addr, enable, addr)
         util.add_mux(self.interfaces[port].wdata, enable, wdata)
-        util.add_mux(self.interfaces[port].wenable, enable, vtypes.Int(1, 1))
-        util.add_mux(self.interfaces[port].enable, enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].wenable, enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].enable, enable, vtypes.Int(1, 1))
 
     def read(self, fsm, addr, port=0):
         """ intrinsic read operation using a shared Seq object """
@@ -221,7 +221,7 @@ def read_dataflow(self, port, addr, length=1,
         read_cond = next_valid_on
         read_enable = vtypes.Ands(data_cond, next_valid_on)
         util.add_mux(self.interfaces[port].addr, read_cond, read_addr)
-        util.add_mux(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
         self.seq.If(data_cond, next_valid_off)(
             last(0),
@@ -327,7 +327,7 @@ def read_dataflow_pattern(self, port, addr, pattern,
         read_cond = next_valid_on
         read_enable = vtypes.Ands(data_cond, next_valid_on)
         util.add_mux(self.interfaces[port].addr, read_cond, read_addr)
-        util.add_mux(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
         self.seq.If(data_cond, next_valid_off)(
             last(0),
@@ -502,7 +502,7 @@ def read_dataflow_reuse(self, port, addr, length=1,
         read_cond = vtypes.Ands(fsm.here, ext_cond)
         read_enable = vtypes.Ands(fsm.here, ext_cond)
         util.add_mux(self.interfaces[port].addr, read_cond, read_addr)
-        util.add_mux(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
         # initial prefetch state
         for n in next_reuse_data:
@@ -517,7 +517,7 @@ def read_dataflow_reuse(self, port, addr, length=1,
             read_cond = fsm.here
             read_enable = fsm.here
             util.add_mux(self.interfaces[port].addr, read_cond, read_addr)
-            util.add_mux(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
             fsm.goto_next()
 
@@ -555,7 +555,7 @@ def read_dataflow_reuse(self, port, addr, length=1,
             read_cond = fsm.here
             read_enable = fsm.here
             util.add_mux(self.interfaces[port].addr, read_cond, read_addr)
-            util.add_mux(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
             fsm.goto_next()
 
@@ -711,7 +711,7 @@ def read_dataflow_reuse_pattern(self, port, addr, pattern,
         read_cond = vtypes.Ands(fsm.here, ext_cond)
         read_enable = vtypes.Ands(fsm.here, ext_cond)
         util.add_mux(self.interfaces[port].addr, read_cond, read_addr)
-        util.add_mux(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
         first = True
         for offset, count, (out_size, out_stride) in zip(offsets, count_list, pattern):
@@ -758,7 +758,7 @@ def read_dataflow_reuse_pattern(self, port, addr, pattern,
                 read_cond = fsm.here
                 read_enable = fsm.here
                 util.add_mux(self.interfaces[port].addr, read_cond, read_addr)
-                util.add_mux(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+                util.add_enable_cond(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
                 if update_count is None:
                     update_count = count == 0
@@ -831,7 +831,7 @@ def read_dataflow_reuse_pattern(self, port, addr, pattern,
                 read_cond = fsm.here
                 read_enable = fsm.here
                 util.add_mux(self.interfaces[port].addr, read_cond, read_addr)
-                util.add_mux(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+                util.add_enable_cond(self.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
                 if offset is not None:
                     fsm.If(update_offset, vtypes.Not(carry))(
@@ -971,8 +971,8 @@ def write_dataflow(self, port, addr, data, length=1,
 
         util.add_mux(self.interfaces[port].addr, write_enable, write_addr)
         util.add_mux(self.interfaces[port].wdata, write_enable, write_data)
-        util.add_mux(self.interfaces[port].wenable, write_enable, vtypes.Int(1, 1))
-        util.add_mux(self.interfaces[port].enable, write_enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].wenable, write_enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].enable, write_enable, vtypes.Int(1, 1))
 
         self.seq.If(ext_cond, counter == 0)(
             write_addr(addr - stride),
@@ -1060,8 +1060,8 @@ def write_dataflow_pattern(self, port, addr, data, pattern,
 
         util.add_mux(self.interfaces[port].addr, write_enable, write_addr)
         util.add_mux(self.interfaces[port].wdata, write_enable, write_data)
-        util.add_mux(self.interfaces[port].wenable, write_enable, vtypes.Int(1, 1))
-        util.add_mux(self.interfaces[port].enable, write_enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].wenable, write_enable, vtypes.Int(1, 1))
+        util.add_enable_cond(self.interfaces[port].enable, write_enable, vtypes.Int(1, 1))
 
         self.seq.If(raw_valid, running)(
             write_addr(offset_addr),
@@ -1754,7 +1754,7 @@ def read_dataflow_interleave(self, port, addr, length=1,
         read_enable = vtypes.Ands(data_cond, next_valid_on)
         for ram, read_addr in zip(self.rams, read_addr_list):
             util.add_mux(ram.interfaces[port].addr, read_cond, read_addr)
-            util.add_mux(ram.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(ram.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
         self.seq.If(data_cond, next_valid_off)(
             last(0),
@@ -1903,7 +1903,7 @@ def read_dataflow_pattern_interleave(self, port, addr, pattern,
         read_enable = vtypes.Ands(data_cond, next_valid_on)
         for ram, read_addr in zip(self.rams, read_addr_list):
             util.add_mux(ram.interfaces[port].addr, read_cond, read_addr)
-            util.add_mux(ram.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(ram.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
         self.seq.If(data_cond, next_valid_off)(
             last(0),
@@ -2114,7 +2114,7 @@ def read_dataflow_block(self, port, addr, length=1, block_size=1,
         read_enable = vtypes.Ands(data_cond, next_valid_on)
         for ram, read_addr in zip(self.rams, read_addr_list):
             util.add_mux(ram.interfaces[port].addr, read_cond, read_addr)
-            util.add_mux(ram.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(ram.interfaces[port].enable, read_enable, vtypes.Int(1, 1))
 
         self.seq.If(data_cond, next_valid_off)(
             last(0),
@@ -2309,8 +2309,8 @@ def write_dataflow_interleave(self, port, addr, data, length=1,
                                                              write_data_list, write_enable_list):
             util.add_mux(ram.interfaces[port].addr, write_enable, write_addr)
             util.add_mux(ram.interfaces[port].wdata, write_enable, write_data)
-            util.add_mux(ram.interfaces[port].wenable, write_enable, vtypes.Int(1, 1))
-            util.add_mux(ram.interfaces[port].enable, write_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(ram.interfaces[port].wenable, write_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(ram.interfaces[port].enable, write_enable, vtypes.Int(1, 1))
 
         self.seq.If(ext_cond, counter == 0)(
             reg_addr(addr - stride),
@@ -2422,8 +2422,8 @@ def write_dataflow_pattern_interleave(self, port, addr, data, pattern,
                                                              write_data_list, write_enable_list):
             util.add_mux(ram.interfaces[port].addr, write_enable, write_addr)
             util.add_mux(ram.interfaces[port].wdata, write_enable, write_data)
-            util.add_mux(ram.interfaces[port].wenable, write_enable, vtypes.Int(1, 1))
-            util.add_mux(ram.interfaces[port].enable, write_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(ram.interfaces[port].wenable, write_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(ram.interfaces[port].enable, write_enable, vtypes.Int(1, 1))
 
         self.seq.If(ext_cond, vtypes.Not(running))(
             running(1)
@@ -2606,8 +2606,8 @@ def write_dataflow_block(self, port, addr, data, length=1, block_size=1,
                                                              write_data_list, write_enable_list):
             util.add_mux(ram.interfaces[port].addr, write_enable, write_addr)
             util.add_mux(ram.interfaces[port].wdata, write_enable, write_data)
-            util.add_mux(ram.interfaces[port].wenable, write_enable, vtypes.Int(1, 1))
-            util.add_mux(ram.interfaces[port].enable, write_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(ram.interfaces[port].wenable, write_enable, vtypes.Int(1, 1))
+            util.add_enable_cond(ram.interfaces[port].enable, write_enable, vtypes.Int(1, 1))
 
         self.seq.If(ext_cond, counter == 0)(
             bank_sel(0),
diff --git a/veriloggen/thread/stream.py b/veriloggen/thread/stream.py
diff --git a/veriloggen/types/util.py b/veriloggen/types/util.py

Original file line number	Diff line number	Diff line change
`@@ -44,7 +44,7 @@ def mkLed():`
`44`	`44`	`count.inc()`
`45`	`45`	`)`
`46`	`46`
`47`		`- util.add_cond(strm.stream_oready, 1, count == 0)`
	`47`	`+ util.add_disable_cond(strm.stream_oready, 1, count == 0)`
`48`	`48`
`49`	`49`	`def comp_stream(size, offset):`
`50`	`50`	`strm.set_source('a', ram_a, offset, size)`
Original file line number	Diff line number	Diff line change
`@@ -64,7 +64,7 @@ def mkLed():`
`64`	`64`	`count.inc()`
`65`	`65`	`)`
`66`	`66`
`67`		`- util.add_cond(strm.stream_oready, 1, count == 0)`
	`67`	`+ util.add_disable_cond(strm.stream_oready, 1, count == 0)`
`68`	`68`
`69`	`69`	`# for sequential`
`70`	`70`	`ram_bufs = [vthread.RAM(m, 'ram_buf' + str(i), clk, rst, datawidth, addrwidth)`
Original file line number	Diff line number	Diff line change
`@@ -58,7 +58,7 @@ def mkLed():`
`58`	`58`	`count.inc()`
`59`	`59`	`)`
`60`	`60`
`61`		`- util.add_cond(strm.stream_oready, 1, count == 0)`
	`61`	`+ util.add_disable_cond(strm.stream_oready, 1, count == 0)`
`62`	`62`
`63`	`63`	`def comp_stream(width, height, offset):`
`64`	`64`	`strm.set_source('dummy_src', ram_dummy_src, offset, width * height * 2 * 2)`
Original file line number	Diff line number	Diff line change
`@@ -61,7 +61,7 @@ def mkLed():`
`61`	`61`	`count.inc()`
`62`	`62`	`)`
`63`	`63`
`64`		`- util.add_cond(strm.stream_oready, 1, count == 0)`
	`64`	`+ util.add_disable_cond(strm.stream_oready, 1, count == 0)`
`65`	`65`
`66`	`66`	`def comp_stream(channel, width, height, offset):`
`67`	`67`	`strm.set_source('dummy_src', ram_dummy_src, offset, channel * width * height * 2 * 2)`
Original file line number	Diff line number	Diff line change
`@@ -53,7 +53,7 @@ def mkLed():`
`53`	`53`	`count.inc()`
`54`	`54`	`)`
`55`	`55`
`56`		`- util.add_cond(strm.stream_oready, 1, count == 0)`
	`56`	`+ util.add_disable_cond(strm.stream_oready, 1, count == 0)`
`57`	`57`
`58`	`58`	`def comp_stream():`
`59`	`59`	`strm.set_source_multipattern('a', ram_a, offsets, patterns)`
Original file line number	Diff line number	Diff line change
`@@ -47,7 +47,7 @@ def mkLed():`
`47`	`47`	`count.inc()`
`48`	`48`	`)`
`49`	`49`
`50`		`- util.add_cond(strm.stream_oready, 1, count == 0)`
	`50`	`+ util.add_disable_cond(strm.stream_oready, 1, count == 0)`
`51`	`51`
`52`	`52`	`def comp_stream(numbins, size, offset):`
`53`	`53`	`for i in range(numbins):`
Original file line number	Diff line number	Diff line change
`@@ -43,7 +43,7 @@ def mkLed():`
`43`	`43`	`count.inc()`
`44`	`44`	`)`
`45`	`45`
`46`		`- util.add_cond(strm.stream_oready, 1, count == 0)`
	`46`	`+ util.add_disable_cond(strm.stream_oready, 1, count == 0)`
`47`	`47`
`48`	`48`	`def comp_stream(size, offset):`
`49`	`49`	`strm.set_source('a', ram_a, offset, size)`
Original file line number	Diff line number	Diff line change
`@@ -37,7 +37,7 @@ def mkLed():`
`37`	`37`	`count.inc()`
`38`	`38`	`)`
`39`	`39`
`40`		`- util.add_cond(strm.stream_oready, 1, count == 0)`
	`40`	`+ util.add_disable_cond(strm.stream_oready, 1, count == 0)`
`41`	`41`
`42`	`42`	`def comp_stream(size, offset):`
`43`	`43`	`strm.set_source('a', ram_a, offset, size)`
Original file line number	Diff line number	Diff line change
`@@ -45,7 +45,7 @@ def mkLed():`
`45`	`45`	`count.inc()`
`46`	`46`	`)`
`47`	`47`
`48`		`- util.add_cond(strm.stream_oready, 1, count == 0)`
	`48`	`+ util.add_disable_cond(strm.stream_oready, 1, count == 0)`
`49`	`49`
`50`	`50`	`def comp_stream(size, offset):`
`51`	`51`	`strm.set_source('a', ram_a, offset, size * 2)`
Original file line number	Diff line number	Diff line change
`@@ -48,7 +48,7 @@ def mkLed():`
`48`	`48`	`count.inc()`
`49`	`49`	`)`
`50`	`50`
`51`		`- util.add_cond(strm.stream_oready, 1, count == 0)`
	`51`	`+ util.add_disable_cond(strm.stream_oready, 1, count == 0)`
`52`	`52`
`53`	`53`	`def comp_stream(size, offset):`
`54`	`54`	`strm.set_source('a', ram_a, offset, size * 2)`