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Submodule for simulation
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‎tests/core/submodule_/sim/Makefile‎

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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/core/submodule_/sim/submodule_sim.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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import collections
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
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os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
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from veriloggen import *
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def mkLed():
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m = Module('blinkled')
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width = m.Parameter('WIDTH', 8)
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clk = m.Input('CLK')
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rst = m.Input('RST')
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led = m.OutputReg('LED', width)
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dummy_out0 = m.Output('dummy_out0', width)
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dummy_out1 = m.Output('dummy_out1', width)
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dummy_out2 = m.Output('dummy_out2', width)
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dummy_in0 = m.Input('dummy_in0', width)
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dummy_in1 = m.Input('dummy_in1', width)
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dummy_in2 = m.Input('dummy_in2', width)
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count = m.Reg('count', 32)
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m.Always(Posedge(clk))(
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If(rst)(
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count(0)
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).Else(
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If(count == 1023)(
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count(0)
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).Else(
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count(count + 1)
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)
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))
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m.Always(Posedge(clk))(
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If(rst)(
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led(0)
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).Else(
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If(count == 1023)(
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led(led + 1)
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)
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))
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m.Always(Posedge(clk))(
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If(rst)(
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).Else(
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Systask('display', "LED:%d count:%d", led, count)
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))
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return m
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def mkTop():
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m = Module('top')
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width = m.Parameter('WIDTH', 8)
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clk = m.Input('CLK')
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rst = m.Input('RST')
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led = m.Output('LED', width)
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sub = Submodule(m, mkLed(), 'inst_blinkled',
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arg_params=(('WIDTH', width),),
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arg_ports=(('LED', led), ('CLK', clk), ('RST', rst)),
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as_io=('dummy_out0', 'dummy_in0'), as_wire=('dummy_out1', 'dummy_in1'))
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return m
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def mkTest():
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m = Module('test')
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# target instance
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led = mkTop()
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uut = Submodule(m, led)
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clk = uut['CLK']
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rst = uut['RST']
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simulation.setup_waveform(m, uut, m.get_vars())
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simulation.setup_clock(m, clk, hperiod=5)
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init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
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init.add(
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Delay(1000 * 100),
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Systask('finish'),
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)
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return m
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if __name__ == '__main__':
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test = mkTest()
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verilog = test.to_verilog(filename='tmp.v')
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#verilog = test.to_verilog()
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print(verilog)
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sim = simulation.Simulator(test)
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rslt = sim.run()
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print(rslt)
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# sim.view_waveform()

‎tests/core/submodule_/sim/test_submodule_sim.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import veriloggen
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import submodule_sim
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expected_verilog = """
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module test #
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(
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parameter inst_top_WIDTH = 8
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)
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(
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);
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reg inst_top_CLK;
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reg inst_top_RST;
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wire [inst_top_WIDTH-1:0] inst_top_LED;
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wire [inst_top_WIDTH-1:0] inst_top_inst_blinkled_dummy_out0;
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reg [inst_top_WIDTH-1:0] inst_top_inst_blinkled_dummy_in0;
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top
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#(
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.WIDTH(inst_top_WIDTH)
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)
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inst_top
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(
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.CLK(inst_top_CLK),
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.RST(inst_top_RST),
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.LED(inst_top_LED),
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.inst_blinkled_dummy_out0(inst_top_inst_blinkled_dummy_out0),
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.inst_blinkled_dummy_in0(inst_top_inst_blinkled_dummy_in0)
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);
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initial begin
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$dumpfile("uut.vcd");
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$dumpvars(0, inst_top, inst_top_CLK, inst_top_RST, inst_top_LED, inst_top_inst_blinkled_dummy_out0, inst_top_inst_blinkled_dummy_in0);
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end
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initial begin
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inst_top_CLK = 0;
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forever begin
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#5 inst_top_CLK = !inst_top_CLK;
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end
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end
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initial begin
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inst_top_RST = 0;
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#100;
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inst_top_RST = 1;
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#100;
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inst_top_RST = 0;
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#100000;
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$finish;
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end
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endmodule
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module top #
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(
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parameter WIDTH = 8
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)
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(
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input CLK,
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input RST,
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output [WIDTH-1:0] LED,
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output [WIDTH-1:0] inst_blinkled_dummy_out0,
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input [WIDTH-1:0] inst_blinkled_dummy_in0
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);
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wire [WIDTH-1:0] inst_blinkled_dummy_out2;
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reg [WIDTH-1:0] inst_blinkled_dummy_in2;
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wire [WIDTH-1:0] inst_blinkled_dummy_out1;
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wire [WIDTH-1:0] inst_blinkled_dummy_in1;
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blinkled
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#(
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.WIDTH(WIDTH)
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)
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inst_blinkled
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(
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.CLK(CLK),
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.RST(RST),
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.LED(LED),
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.dummy_out0(inst_blinkled_dummy_out0),
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.dummy_out1(inst_blinkled_dummy_out1),
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.dummy_out2(inst_blinkled_dummy_out2),
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.dummy_in0(inst_blinkled_dummy_in0),
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.dummy_in1(inst_blinkled_dummy_in1),
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.dummy_in2(inst_blinkled_dummy_in2)
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);
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endmodule
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module blinkled #
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(
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parameter WIDTH = 8
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)
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(
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input CLK,
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input RST,
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output reg [WIDTH-1:0] LED,
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output [WIDTH-1:0] dummy_out0,
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output [WIDTH-1:0] dummy_out1,
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output [WIDTH-1:0] dummy_out2,
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input [WIDTH-1:0] dummy_in0,
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input [WIDTH-1:0] dummy_in1,
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input [WIDTH-1:0] dummy_in2
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);
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reg [32-1:0] count;
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always @(posedge CLK) begin
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if(RST) begin
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count <= 0;
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end else begin
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if(count == 1023) begin
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count <= 0;
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end else begin
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count <= count + 1;
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end
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end
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end
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always @(posedge CLK) begin
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if(RST) begin
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LED <= 0;
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end else begin
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if(count == 1023) begin
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LED <= LED + 1;
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end
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end
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end
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always @(posedge CLK) begin
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if(RST) begin
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end else begin
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$display("LED:%d count:%d", LED, count);
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end
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end
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endmodule
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"""
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def test():
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test_module = submodule_sim.mkTest()
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code = test_module.to_verilog()
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from pyverilog.vparser.parser import VerilogParser
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
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parser = VerilogParser()
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expected_ast = parser.parse(expected_verilog)
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codegen = ASTCodeGenerator()
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expected_code = codegen.visit(expected_ast)
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assert(expected_code == code)

‎veriloggen/simulation/simulation.py‎

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import veriloggen.core.vtypes as vtypes
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import veriloggen.core.module as module
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import veriloggen.core.submodule as submodule
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def setup_waveform(m, *uuts):
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if isinstance(u, vtypes._Variable) and u.length is not None:
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continue
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new_uuts.append(u)
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elif isinstance(uut, submodule.Submodule):
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new_uuts.append(uut.inst)
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else:
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if isinstance(uut, vtypes._Variable) and uut.length is not None:
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continue

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