bram without reset

Author: shtaxxx

examples/dataflow_matmul_bram/dataflow_matmul_bram.py

@@ -29,7 +29,6 @@ def mkBram(datawidth=32, addrwidth=10, numports=2):
     m = Module('BRAM%d' % numports)
 
     clk = m.Input('CLK')
-    rst = m.Input('RST')
     ports = []
     for i in range(numports):
         addr = m.Input('ADDR%d' % i, addrwidth)
@@ -80,7 +79,7 @@ def mkMatmulBram(n=16, datawidth=32):
         int_ports.append( [addr, din, we, dout] )
 
     for i in range(3):
-        ports = [ clk, rst ] + ext_ports[i] + int_ports[i]
+        ports = [ clk ] + ext_ports[i] + int_ports[i]
         m.Instance(bram, 'inst_bram%d' % i, ports=ports)
 
     xaddr = m.Reg('xaddr', addrwidth, initval=0)

examples/dataflow_matmul_bram/test_dataflow_matmul_bram.py

@@ -219,7 +219,6 @@
   inst_bram0
   (
     .CLK(CLK),
-    .RST(RST),
     .ADDR0(bram_addr0),
     .DIN0(bram_din0),
     .WE0(bram_we0),
@@ -235,7 +234,6 @@
   inst_bram1
   (
     .CLK(CLK),
-    .RST(RST),
     .ADDR0(bram_addr1),
     .DIN0(bram_din1),
     .WE0(bram_we1),
@@ -251,7 +249,6 @@
   inst_bram2
   (
     .CLK(CLK),
-    .RST(RST),
     .ADDR0(bram_addr2),
     .DIN0(bram_din2),
     .WE0(bram_we2),
@@ -408,7 +405,6 @@
 module BRAM2
 (
   input CLK,
-  input RST,
   input [8-1:0] ADDR0,
   input [32-1:0] DIN0,
   input WE0,