RST_X -> RESETN

Author: shtaxxx

tests/extension/thread_/axi_dma_active_low_reset/thread_axi_dma_active_low_reset.py

@@ -17,11 +17,11 @@ def mkLed():
     clk = m.Input('CLK')
 
     # active low
-    rst_x = m.Input('RST_X')
+    resetn = m.Input('RESETN')
 
     # active low -> active high
     rst = m.Wire('RST')
-    rst.assign(Not(rst_x))
+    rst.assign(Not(resetn))
 
     datawidth = 32
     addrwidth = 10
@@ -113,11 +113,11 @@ def mkTest(memimg_name=None):
     clk = ports['CLK']
 
     # active low
-    rst_x = ports['RST_X']
+    resetn = ports['RESETN']
 
     # active low -> active high
     rst = m.Wire('RST')
-    rst.assign(Not(rst_x))
+    rst.assign(Not(resetn))
 
     memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
@@ -128,7 +128,7 @@ def mkTest(memimg_name=None):
 
     #simulation.setup_waveform(m, uut)
     simulation.setup_clock(m, clk, hperiod=5)
-    init = simulation.setup_reset(m, rst_x, m.make_reset(), period=100, polarity='low')
+    init = simulation.setup_reset(m, resetn, m.make_reset(), period=100, polarity='low')
 
     init.add(
         Delay(1000000),

tests/extension/thread_/ipxact_axi_active_low_reset/thread_ipxact_axi_active_low_reset.py

@@ -19,11 +19,11 @@ def mkLed():
     clk = m.Input('CLK')
 
     # active low
-    rst_x = m.Input('RST_X')
+    resetn = m.Input('RESETN')
 
     # active low -> active high
     rst = m.Wire('RST')
-    rst.assign(Not(rst_x))
+    rst.assign(Not(resetn))
 
     datawidth = 32
     addrwidth = 10
@@ -128,11 +128,11 @@ def mkTest(memimg_name=None):
     clk = ports['CLK']
 
     # active low
-    rst_x = ports['RST_X']
+    resetn = ports['RESETN']
 
     # active low -> active high
     rst = m.Wire('RST')
-    rst.assign(Not(rst_x))
+    rst.assign(Not(resetn))
 
     memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
     memory.connect(ports, 'myaxi')
@@ -169,7 +169,7 @@ def ctrl():
 
     #simulation.setup_waveform(m, uut)
     simulation.setup_clock(m, clk, hperiod=5)
-    init = simulation.setup_reset(m, rst_x, m.make_reset(), period=100, polarity='low')
+    init = simulation.setup_reset(m, resetn, m.make_reset(), period=100, polarity='low')
 
     init.add(
         Delay(1000000),
@@ -215,5 +215,5 @@ def run(filename='tmp.v', simtype='iverilog', outputfile=None):
 
     m = mkLed()
     ipxact.to_ipxact(m,
-                     clk_ports=[('CLK', ('RST_X',))],
-                     rst_ports=[('RST_X', 'ACTIVE_LOW')])
+                     clk_ports=[('CLK', ('RESETN',))],
+                     rst_ports=[('RESETN', 'ACTIVE_LOW')])