Boundary condition check for math.log operator applied to 0.

Author: shtaxxx

veriloggen/stream/stream.py

@@ -247,7 +247,7 @@ def implement(self, m=None, clock=None, reset=None, aswire=None, seq_name=None):
     def add_dump(self, m, seq, input_vars, output_vars, all_vars):
         pipeline_depth = self.pipeline_depth()
         log_pipeline_depth = max(
-            int(math.ceil(math.log(pipeline_depth, 10))), 1)
+            int(math.ceil(math.log(max(pipeline_depth, 10), 10))), 1)
 
         seq(
             self.dump_step(1)

veriloggen/stream/stypes.py

@@ -1025,10 +1025,6 @@ def _set_attributes(self):
         self.signed = False
 
     def _implement(self, m, seq, svalid=None, senable=None):
-        if self.latency != 1:
-            raise ValueError("Latency mismatch '%d' vs '%s'" %
-                             (self.latency, 1))
-
         width = self.bit_length()
         signed = False
 
@@ -2718,10 +2714,29 @@ def _implement(self, m, seq, svalid=None, senable=None):
         signed = self.get_signed()
         rdata = self.output_var.read()
 
-        data = m.Reg(self.name('data'), width, initval=0, signed=signed)
-        self.sig_data = data
+        if self.latency == 0:
+            data = m.Wire(self.name('data'), width, signed=signed)
+            data.assign(rdata)
+            self.sig_data = data
 
-        seq(data(rdata), cond=senable)
+        elif self.latency == 1:
+            data = m.Reg(self.name('data'), width, initval=0, signed=signed)
+            self.sig_data = data
+            seq(data(rdata), cond=senable)
+
+        else:
+            prev_data = None
+
+            for i in range(self.latency):
+                data = m.Reg(self.name('data_d%d' % i),
+                             width, initval=0, signed=signed)
+                if i == 0:
+                    seq(data(rdata), cond=senable)
+                else:
+                    seq(data(prev_data), cond=senable)
+                prev_data = data
+
+            self.sig_data = data
 
 
 class RingBuffer(_UnaryOperator):

veriloggen/thread/stream.py

@@ -1061,7 +1061,7 @@ def run(self, fsm):
             if sub.substrm.sink_wait_count is None:
                 sub.substrm.sink_wait_count = sub.substrm.module.Reg(
                     '_'.join(['', sub.substrm.name, 'sink_wait_count']),
-                    int(math.ceil(math.log(num_wdelay, 2))), initval=0)
+                    int(math.ceil(math.log(max(num_wdelay, 2), 2))), initval=0)
 
             sub.substrm.fsm.seq.If(sub.substrm.sink_wait_count == 1,
                                    vtypes.Not(start_cond),
@@ -1085,7 +1085,7 @@ def run(self, fsm):
         if self.sink_wait_count is None:
             self.sink_wait_count = self.module.Reg(
                 '_'.join(['', self.name, 'sink_wait_count']),
-                int(math.ceil(math.log(num_wdelay, 2))), initval=0)
+                int(math.ceil(math.log(max(num_wdelay, 2), 2))), initval=0)
 
         self.fsm.seq.If(self.sink_wait_count == 1,
                         vtypes.Not(start_cond),
@@ -1213,7 +1213,7 @@ def _setup_source_ram(self, ram, var, port, set_cond):
     def _setup_source_ram_dump(self, ram, var, read_enable, read_data):
         pipeline_depth = self.pipeline_depth()
         log_pipeline_depth = max(
-            int(math.ceil(math.log(pipeline_depth, 10))), 1)
+            int(math.ceil(math.log(max(pipeline_depth, 10), 10))), 1)
 
         addr_base = (ram.dump_addr_base if hasattr(ram, 'dump_addr_base') else
                      self.dump_base)
@@ -1451,7 +1451,7 @@ def _make_source_multipattern_vars(self, var, name):
 
         var.source_multipat_num_patterns = self.module.Reg(
             '_source_%s_multipat_num_patterns' % prefix,
-            int(math.ceil(math.log(self.max_multipattern_length, 2))), initval=0)
+            int(math.ceil(math.log(max(self.max_multipattern_length, 2), 2))), initval=0)
         var.source_multipat_offsets = [
             self.module.Reg('_source_%s_multipat_%d_offset' % (prefix, j),
                             self.addrwidth, initval=0)
@@ -1661,7 +1661,7 @@ def _setup_sink_ram(self, ram, var, port, set_cond):
     def _setup_sink_ram_dump(self, ram, var, write_enable):
         pipeline_depth = self.pipeline_depth()
         log_pipeline_depth = max(
-            int(math.ceil(math.log(pipeline_depth, 10))), 1)
+            int(math.ceil(math.log(max(pipeline_depth, 10), 10))), 1)
 
         addr_base = (ram.dump_addr_base if hasattr(ram, 'dump_addr_base') else
                      self.dump_base)
@@ -1886,7 +1886,7 @@ def _make_sink_multipattern_vars(self, var, name):
 
         var.sink_multipat_num_patterns = self.module.Reg(
             '_sink_%s_multipat_num_patterns' % prefix,
-            int(math.ceil(math.log(self.max_multipattern_length, 2))), initval=0)
+            int(math.ceil(math.log(max(self.max_multipattern_length, 2), 2))), initval=0)
         var.sink_multipat_offsets = [
             self.module.Reg('_sink_%s_multipat_%d_offset' % (prefix, j),
                             self.addrwidth, initval=0)