bug fix of Shift Right Arithmetic op in Thread

Author: shtaxxx

tests/extension/thread_/sra/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/thread_/sra/test_thread_sra.py

@@ -0,0 +1,104 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import veriloggen
+import thread_sra
+
+expected_verilog = """
+module test;
+
+  reg CLK;
+  reg RST;
+  wire [8-1:0] LED;
+
+  blinkled
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .LED(LED)
+  );
+
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = !CLK;
+    end
+  end
+
+
+  initial begin
+    RST = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #10000;
+    $finish;
+  end
+
+
+endmodule
+
+
+
+module blinkled
+(
+  input CLK,
+  input RST,
+  output reg [8-1:0] LED
+);
+
+  reg [32-1:0] th_blink;
+  localparam th_blink_init = 0;
+  reg signed [32-1:0] _th_blink_a_0;
+  reg signed [32-1:0] _th_blink_b_1;
+  localparam th_blink_1 = 1;
+  localparam th_blink_2 = 2;
+  localparam th_blink_3 = 3;
+  localparam th_blink_4 = 4;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      th_blink <= th_blink_init;
+      _th_blink_a_0 <= 0;
+      _th_blink_b_1 <= 0;
+    end else begin
+      case(th_blink)
+        th_blink_init: begin
+          th_blink <= th_blink_1;
+        end
+        th_blink_1: begin
+          _th_blink_a_0 <= -'sd16;
+          th_blink <= th_blink_2;
+        end
+        th_blink_2: begin
+          _th_blink_b_1 <= _th_blink_a_0 >>> 2;
+          th_blink <= th_blink_3;
+        end
+        th_blink_3: begin
+          $display("%d %d", _th_blink_a_0, _th_blink_b_1);
+          th_blink <= th_blink_4;
+        end
+      endcase
+    end
+  end
+
+
+endmodule
+"""
+
+
+def test():
+    veriloggen.reset()
+    test_module = thread_sra.mkTest()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

tests/extension/thread_/sra/thread_sra.py

@@ -0,0 +1,67 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', 8, initval=0)
+
+    def blink():
+        a = -16
+        b = a >> 2
+        print(a, b)
+
+    th = vthread.Thread(m, 'th_blink', clk, rst, blink)
+    fsm = th.start()
+
+    return m
+
+
+def mkTest():
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(10000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)
+
+    sim = simulation.Simulator(test)
+    rslt = sim.run()
+    print(rslt)

veriloggen/thread/operator.py

@@ -14,7 +14,7 @@
     ast.Mod: vtypes.Mod,
     ast.Pow: vtypes.Power,
     ast.LShift: vtypes.Sll,
-    ast.RShift: vtypes.Srl,
+    ast.RShift: vtypes.Sra,
     ast.BitOr: vtypes.Or,
     ast.BitXor: vtypes.Xor,
     ast.BitAnd: vtypes.And,
@@ -51,7 +51,7 @@ def getVeriloggenOp(op):
     ast.Mod: '__mod__',
     ast.Pow: '__pow__',
     ast.LShift: '__lshift__',
-    ast.RShift: '__rshift__',
+    ast.RShift: None,
     ast.BitOr: '__or__',
     ast.BitXor: '__xor__',
     ast.BitAnd: '__and__',