draw_graph method for Substream with input port names

Author: shtaxxx

tests/extension/thread_/stream_graph_substream/thread_stream_graph_substream.py

@@ -187,7 +187,7 @@ def comp(size):
     fsm = th.start(32)
 
     try:
-        strm.draw_graph()
+        actstrm.draw_graph()
     except:
         pass
 

veriloggen/stream/graph.py

@@ -191,7 +191,7 @@ def visit__SpecialOperator(self, node):
 
         for i, arg in enumerate(node.args):
             a = self.visit(arg)
-            self.graph.add_edge(a, node, label='p%d' % i)
+            self.graph.add_edge(a, node, label='a%d' % i)
 
         if node.start_stage is not None:
             self._set_rank(node.start_stage + 1, node)
@@ -231,6 +231,28 @@ def visit__Accumulator(self, node):
         self._add_output(node, prev)
         return prev
 
+    def visit_Substream(self, node):
+        label = self._get_label(node)
+        shape = self._get_shape(node)
+        color = self._get_color(node)
+        style = self._get_style(node)
+        peripheries = self._get_peripheries(node)
+        self.graph.add_node(node,
+                            label=label, shape=shape,
+                            color=color, style=style,
+                            peripheries=peripheries)
+
+        for arg, name in zip(node.args, node.conds.keys()):
+            a = self.visit(arg)
+            self.graph.add_edge(a, node, label=name)
+
+        if node.start_stage is not None:
+            self._set_rank(node.start_stage + 1, node)
+
+        prev = self._add_gap(node, label)
+        self._add_output(node, prev)
+        return prev
+
     def visit_RingBuffer(self, node):
         label = self._get_label(node)
         shape = self._get_shape(node)

veriloggen/stream/scheduler.py

@@ -136,6 +136,9 @@ def visit__Accumulator(self, node):
         node._set_end_stage(end)
         return end
 
+    def visit_Substream(self, node):
+        return self.visit__SpecialOperator(node)
+
     def visit_RingBuffer(self, node):
         if node._has_start_stage():
             return node._get_end_stage()

veriloggen/stream/visitor.py

@@ -27,6 +27,9 @@ def visit(self, node):
         return rslt
 
     def _visit(self, node):
+        if isinstance(node, stypes.Substream):
+            return self.visit_Substream(node)
+
         if isinstance(node, stypes.RingBuffer):
             return self.visit_RingBuffer(node)
 
@@ -76,6 +79,9 @@ def visit__SpecialOperator(self, node):
     def visit__Accumulator(self, node):
         raise NotImplementedError()
 
+    def visit_Substream(self, node):
+        raise NotImplementedError()
+
     def visit_RingBuffer(self, node):
         raise NotImplementedError()
 
@@ -125,6 +131,9 @@ def visit__Accumulator(self, node):
         reset = self.visit(node.reset) if node.reset is not None else set()
         return right | size | initval | enable | reset
 
+    def visit_Substream(self, node):
+        return self.visit__SpecialOperator(node)
+
     def visit_RingBuffer(self, node):
         right = self.visit(node.right)
         enable = self.visit(node.enable) if node.enable is not None else set()
@@ -192,6 +201,9 @@ def visit__Accumulator(self, node):
         mine = set([node]) if node._has_output() else set()
         return right | size | initval | enable | reset | mine
 
+    def visit_Substream(self, node):
+        return self.visit__SpecialOperator(node)
+
     def visit_RingBuffer(self, node):
         right = self.visit(node.right)
         enable = self.visit(node.enable) if node.enable is not None else set()
@@ -267,6 +279,9 @@ def visit__Accumulator(self, node):
         mine = set([node])
         return right | size | initval | enable | reset | mine
 
+    def visit_Substream(self, node):
+        return self.visit__SpecialOperator(node)
+
     def visit_RingBuffer(self, node):
         right = self.visit(node.right)
         enable = self.visit(node.enable) if node.enable is not None else set()