stream_extern_ram

shtaxxx · shtaxxx · commit 8fa5ae40819a · 2019-07-11T12:16:39.000+09:00
diff --git a/tests/extension/thread_/stream_extern/thread_stream_extern.py b/tests/extension/thread_/stream_extern/thread_stream_extern.py
@@ -37,7 +37,7 @@ def mkLed():
     strm.sink(b, 'b')
 
     def comp_stream(size, offset):
-        strm.set_source('a', ram_a, offset, size * 2)
+        strm.set_source('a', ram_a, offset, size)
         strm.set_sink('b', ram_b, offset, size)
         strm.run()
         strm.join()
@@ -65,13 +65,13 @@ def check(size, offset_stream, offset_seq):
     def comp(size):
         # stream
         offset = 0
-        myaxi.dma_read(ram_a, offset, 0, size * 2)
+        myaxi.dma_read(ram_a, offset, 0, size)
         comp_stream(size, offset)
         myaxi.dma_write(ram_b, offset, 1024, size)
 
         # sequential
         offset = size * 4
-        myaxi.dma_read(ram_a, offset, 0, size * 2)
+        myaxi.dma_read(ram_a, offset, 0, size)
         comp_sequential(size, offset)
         myaxi.dma_write(ram_b, offset, 1024 * 2, size)
 
diff --git a/tests/extension/thread_/stream_extern_ram/Makefile b/tests/extension/thread_/stream_extern_ram/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
diff --git a/tests/extension/thread_/stream_extern_ram/test_thread_stream_extern_ram.py b/tests/extension/thread_/stream_extern_ram/test_thread_stream_extern_ram.py
@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_extern_ram
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_extern_ram.run(filename=None, simtype=simtype,
+                                        outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')
diff --git a/tests/extension/thread_/stream_extern_ram/thread_stream_extern_ram.py b/tests/extension/thread_/stream_extern_ram/thread_stream_extern_ram.py
@@ -0,0 +1,144 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+
+    ram_ext = vthread.RAM(m, 'ram_ext', clk, rst, datawidth, addrwidth, numports=2)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+
+    a = strm.source('a')
+    r_addr = strm.Counter() - 1  # 0, 1, 2, ...
+
+    r = strm.ReadRAM(ram_ext, r_addr, port=1)
+    b = r + 100
+
+    strm.sink(b, 'b')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_sink('b', ram_b, offset, size)
+        strm.run()
+        strm.join()
+
+    def comp_sequential(size, offset):
+        for i in range(size):
+            r_addr = ram_a.read(i)
+            r = ram_a.read(r_addr)
+            b = r + 100
+            ram_b.write(i + offset, b)
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_b.read(i + offset_stream)
+            sq = ram_b.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        for i in range(size):
+            ram_a.write(i, size - i - 1)
+
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_ext, offset, 0, size)
+        comp_stream(size, offset)
+        myaxi.dma_write(ram_b, offset, 1024, size)
+
+        # sequential
+        offset = size * 4
+        myaxi.dma_read(ram_ext, offset, 0, size)
+        comp_sequential(size, offset)
+        myaxi.dma_write(ram_b, offset, 1024 * 2, size)
+
+        # verification
+        check(size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)
diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py
@@ -3135,8 +3135,17 @@ def _implement(self, m, seq, svalid=None, senable=None):
 class FromExtern(_UnaryOperator):
     latency = 1
 
-    def __init__(self, right, latency=1):
+    def __init__(self, right, width=None, point=None, signed=True, latency=1):
         _UnaryOperator.__init__(self, right)
+
+        if width is not None:
+            self.width = width
+
+        if point is not None:
+            self.point = point
+
+        self.signed = signed
+
         self.latency = latency
 
         self.graph_label = 'FromExtern'
@@ -3160,6 +3169,50 @@ def _implement(self, m, seq, svalid=None, senable=None):
         self.sig_data = data
 
 
+class ReadRAM(_UnaryOperator):
+    latency = 1
+
+    def __init__(self, ram, addr, width=None, point=None, signed=True, port=0):
+        _UnaryOperator.__init__(self, addr)
+
+        self.ram = ram
+
+        if width is None:
+            self.width = ram.datawidth
+        else:
+            self.width = width
+
+        if point is None:
+            self.point = 0 if not hasattr(ram, 'point') else ram.point
+        else:
+            self.point = point
+
+        self.signed = signed
+        self.port = port
+
+        self.graph_label = 'Read ' + ram.name if hasattr(ram, 'name') else 'Read RAM'
+        self.graph_shape = 'box'
+
+    def _implement(self, m, seq, svalid=None, senable=None):
+        datawidth = self.bit_length()
+        addrwidth = int(log(self.ram.length, 2))
+        signed = self.get_signed()
+
+        rdata = m.Wire(self.name('rdata'), datawidth, signed=signed)
+
+        raddr = m.Wire(self.name('raddr'), addrwidth)
+        raddr.assign(self.right.sig_data)
+
+        if hasattr(self.ram, 'connect'):
+            self.ram.connect(self.port, raddr, 0, 0)
+            rdata.assign(self.ram.rdata(self.port))
+
+        elif hasattr(self.ram, 'connect_rtl'):
+            self.ram.connect_rtl(self.port, raddr, 0, 0, rdata)
+
+        self.sig_data = rdata
+
+
 def make_condition(*cond, **kwargs):
     ready = kwargs['ready'] if 'ready' in kwargs else None
 
