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2 parents 9d2525a + 1db8101 commit 90caa2aCopy full SHA for 90caa2a
veriloggen/stream/stypes.py
@@ -2549,16 +2549,6 @@ def _implement(self, m, seq, svalid=None, senable=None):
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seq(data(reset_value), cond=reset_cond)
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-class Predicate(_Accumulator):
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- ops = (lambda x, y: y, )
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-
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- def __init__(self, value, condition, initval=0,
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- reset=None, width=32, signed=True):
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- size = 1
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- _Accumulator.__init__(self, value, size, initval,
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- condition, reset, width, signed)
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class ReduceAdd(_Accumulator):
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ops = (vtypes.Plus, )
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@@ -3237,6 +3227,18 @@ def write(self, fsm, value):
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)
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+class Predicate(Reg):
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+ __intrinsics__ = ()
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+
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+ def __init__(self, data, when):
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+ Reg.__init__(self, data, when)
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+ self.graph_label = 'Predicate'
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+ self.graph_shape = 'box'
+ def write(self, fsm, value):
+ raise NotImplementedError()
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class ReadRAM(_SpecialOperator):
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latency = 3
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