examples with RTL simulations are updated.

Author: shtaxxx

examples/simulation_verilator/simulation_verilator.py

@@ -88,7 +88,7 @@ def check(matrix_size, a_offset, b_offset, c_offset):
     return m
 
 
-def mkTest():
+def mkTest(memimg_name=None):
     m = Module('test')
 
     matrix_size = 16
@@ -104,7 +104,8 @@ def mkTest():
     rst = ports['RST']
 
     # memory image
-    memname = 'mymem.out'
+    if memimg_name is None:
+        memimg_name = 'mymem.out'
 
     def fwrite(f, value):
         s = '%08x' % value
@@ -113,7 +114,7 @@ def fwrite(f, value):
         f.write('%s\n' % s[2:4])
         f.write('%s\n' % s[0:2])
 
-    with open(memname, 'w') as f:
+    with open(memimg_name, 'w') as f:
         # ram_a
         addr = 0
         nv = 1
@@ -155,7 +156,7 @@ def fwrite(f, value):
         for i in range(2 ** 20 - addr):
             f.write('%s\n' % '00')
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg=memname)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg=memimg_name)
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',

examples/simulation_verilator/test_simulation_verilator.py

@@ -1,5 +1,6 @@
 from __future__ import absolute_import
 from __future__ import print_function
+import os
 import veriloggen
 import simulation_verilator
 
@@ -50,7 +51,7 @@
   reg [8-1:0] _memory_mem [0:2**20-1];
 
   initial begin
-    $readmemh("mymem.out", _memory_mem);
+    $readmemh("memimg_test_simulation_verilator.out", _memory_mem);
   end
 
   reg [32-1:0] _memory_fsm;
@@ -1893,7 +1894,8 @@
 
 def test():
     veriloggen.reset()
-    test_module = simulation_verilator.mkTest()
+    memimg_name = 'memimg_' + os.path.splitext(os.path.basename(__file__))[0] + '.out'
+    test_module = simulation_verilator.mkTest(memimg_name=memimg_name)
     verilog = veriloggen.simulation.to_verilator_code(
         test_module, [test_module])
     cpp = veriloggen.simulation.to_verilator_cpp(test_module, 'out')

examples/thread_matmul/test_thread_matmul.py

@@ -1,6 +1,7 @@
 from __future__ import absolute_import
 from __future__ import print_function
 
+import os
 import veriloggen
 import thread_matmul
 
@@ -10,7 +11,8 @@ def test(request):
 
     simtype = request.config.getoption('--sim')
 
-    rslt = thread_matmul.run(filename=None, simtype=simtype)
+    rslt = thread_matmul.run(filename=None, simtype=simtype,
+                             outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
 
     verify_rslt = rslt.splitlines()[-1]
     assert(verify_rslt == '# verify: PASSED')

examples/thread_matmul/thread_matmul.py

@@ -96,7 +96,7 @@ def check(matrix_size, a_offset, b_offset, c_offset):
     return m
 
 
-def mkTest():
+def mkTest(memimg_name=None):
     matrix_size = 16
 
     a_shape = (matrix_size, matrix_size)
@@ -147,8 +147,10 @@ def mkTest():
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg=mem,
-                                mem_datawidth=8 * axi_wordsize)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
+                                mem_datawidth=8 * axi_wordsize,
+                                memimg=mem, memimg_name=memimg_name)
+                                
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
@@ -167,15 +169,20 @@ def mkTest():
     return m
 
 
-def run(filename='tmp.v', simtype='iverilog'):
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
 
-    test = mkTest()
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
 
     if filename is not None:
         test.to_verilog(filename)
 
     sim = simulation.Simulator(test, sim=simtype)
-    rslt = sim.run(outputfile=simtype + '.out')
+    rslt = sim.run(outputfile=outputfile)
     lines = rslt.splitlines()
     if simtype == 'verilator' and lines[-1].startswith('-'):
         rslt = '\n'.join(lines[:-1])

examples/thread_matmul_ipcore/test_thread_matmul_ipcore.py

@@ -1,6 +1,7 @@
 from __future__ import absolute_import
 from __future__ import print_function
 
+import os
 import veriloggen
 import thread_matmul_ipcore
 
@@ -10,7 +11,8 @@ def test(request):
 
     simtype = request.config.getoption('--sim')
 
-    rslt = thread_matmul_ipcore.run(filename=None, simtype=simtype)
+    rslt = thread_matmul_ipcore.run(filename=None, simtype=simtype,
+                                    outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
 
     verify_rslt = rslt.splitlines()[-1]
     assert(verify_rslt == '# verify: PASSED')

examples/thread_matmul_ipcore/thread_matmul_ipcore.py

@@ -77,7 +77,7 @@ def comp(matrix_size, a_offset, b_offset, c_offset):
     return m
 
 
-def mkTest():
+def mkTest(memimg_name=None):
 
     a_shape = (matrix_size, matrix_size)
     b_shape = (matrix_size, matrix_size)
@@ -127,8 +127,10 @@ def mkTest():
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg=mem,
-                                mem_datawidth=8 * axi_wordsize)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
+                                mem_datawidth=8 * axi_wordsize,
+                                memimg=mem, memimg_name=memimg_name)
+
     memory.connect(ports, 'maxi')
 
     # AXI-Slave controller
@@ -215,15 +217,20 @@ def ctrl():
     return m
 
 
-def run(filename='tmp.v', simtype='iverilog'):
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
 
-    test = mkTest()
+    test = mkTest(memimg_name=memimg_name)
 
     if filename is not None:
         test.to_verilog(filename)
 
     sim = simulation.Simulator(test, sim=simtype)
-    rslt = sim.run(outputfile=simtype + '.out')
+    rslt = sim.run(outputfile=outputfile)
     lines = rslt.splitlines()
     if simtype == 'verilator' and lines[-1].startswith('-'):
         rslt = '\n'.join(lines[:-1])

examples/thread_matmul_narrow/test_thread_matmul_narrow.py

@@ -1,6 +1,7 @@
 from __future__ import absolute_import
 from __future__ import print_function
 
+import os
 import veriloggen
 import thread_matmul_narrow
 
@@ -10,7 +11,8 @@ def test(request):
 
     simtype = request.config.getoption('--sim')
 
-    rslt = thread_matmul_narrow.run(filename=None, simtype=simtype)
+    rslt = thread_matmul_narrow.run(filename=None, simtype=simtype,
+                                    outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
 
     verify_rslt = rslt.splitlines()[-1]
     assert(verify_rslt == '# verify: PASSED')

examples/thread_matmul_narrow/thread_matmul_narrow.py

@@ -97,7 +97,7 @@ def check(matrix_size, a_offset, b_offset, c_offset):
     return m
 
 
-def mkTest():
+def mkTest(memimg_name=None):
     matrix_size = 16
 
     a_shape = (matrix_size, matrix_size)
@@ -148,8 +148,10 @@ def mkTest():
     clk = ports['CLK']
     rst = ports['RST']
 
-    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg=mem,
-                                mem_datawidth=8 * axi_wordsize)
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
+                                mem_datawidth=8 * axi_wordsize,
+                                memimg=mem, memimg_name=memimg_name)
+
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
@@ -168,15 +170,20 @@ def mkTest():
     return m
 
 
-def run(filename='tmp.v', simtype='iverilog'):
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
 
-    test = mkTest()
+    test = mkTest(memimg_name=memimg_name)
 
     if filename is not None:
         test.to_verilog(filename)
 
     sim = simulation.Simulator(test, sim=simtype)
-    rslt = sim.run(outputfile=simtype + '.out')
+    rslt = sim.run(outputfile=outputfile)
     lines = rslt.splitlines()
     if simtype == 'verilator' and lines[-1].startswith('-'):
         rslt = '\n'.join(lines[:-1])

examples/thread_matmul_wide/test_thread_matmul_wide.py

@@ -1,6 +1,7 @@
 from __future__ import absolute_import
 from __future__ import print_function
 
+import os
 import veriloggen
 import thread_matmul_wide
 
@@ -10,7 +11,8 @@ def test(request):
 
     simtype = request.config.getoption('--sim')
 
-    rslt = thread_matmul_wide.run(filename=None, simtype=simtype)
+    rslt = thread_matmul_wide.run(filename=None, simtype=simtype,
+                                  outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
 
     verify_rslt = rslt.splitlines()[-1]
     assert(verify_rslt == '# verify: PASSED')

examples/thread_matmul_wide/thread_matmul_wide.py

@@ -96,7 +96,7 @@ def check(matrix_size, a_offset, b_offset, c_offset):
     return m
 
 
-def mkTest():
+def mkTest(memimg_name=None):
     matrix_size = 16
 
     a_shape = (matrix_size, matrix_size)
@@ -150,7 +150,8 @@ def mkTest():
     memory = axi.AxiMemoryModel(m, 'memory', clk, rst,
                                 datawidth=8 * axi_wordsize,
                                 mem_datawidth=8 * axi_wordsize,
-                                memimg=mem)
+                                memimg=mem, memimg_name=memimg_name)
+
     memory.connect(ports, 'myaxi')
 
     uut = m.Instance(led, 'uut',
@@ -169,15 +170,20 @@ def mkTest():
     return m
 
 
-def run(filename='tmp.v', simtype='iverilog'):
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
 
-    test = mkTest()
+    test = mkTest(memimg_name=memimg_name)
 
     if filename is not None:
         test.to_verilog(filename)
 
     sim = simulation.Simulator(test, sim=simtype)
-    rslt = sim.run(outputfile=simtype + '.out')
+    rslt = sim.run(outputfile=outputfile)
     lines = rslt.splitlines()
     if simtype == 'verilator' and lines[-1].startswith('-'):
         rslt = '\n'.join(lines[:-1])