active low reset

shtaxxx · shtaxxx · commit af1cf46ac35a · 2019-03-26T15:17:11.000+09:00
diff --git a/tests/extension/thread_/axi_dma_active_low_reset/Makefile b/tests/extension/thread_/axi_dma_active_low_reset/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
diff --git a/tests/extension/thread_/axi_dma_active_low_reset/test_thread_axi_dma_active_low_reset.py b/tests/extension/thread_/axi_dma_active_low_reset/test_thread_axi_dma_active_low_reset.py
@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_axi_dma_active_low_reset
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_axi_dma_active_low_reset.run(filename=None, simtype=simtype,
+                                               outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')
diff --git a/tests/extension/thread_/axi_dma_active_low_reset/thread_axi_dma_active_low_reset.py b/tests/extension/thread_/axi_dma_active_low_reset/thread_axi_dma_active_low_reset.py
@@ -0,0 +1,162 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    # active low reset
+    rst_x = m.Input('RST_X')
+
+    # active low -> active high
+    rst = m.Wire('RST')
+    rst.assign(Not(rst_x))
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth,
+                         num_cmd_delay=1, num_data_delay=1)
+    myram = vthread.RAM(m, 'myram', clk, rst, datawidth, addrwidth,
+                        numports=2)
+
+    all_ok = m.TmpReg(initval=0)
+
+    def blink(size):
+        all_ok.value = True
+
+        for i in range(4):
+            print('# iter %d start' % i)
+            # Test for 4KB boundary check
+            offset = i * 1024 * 16 + (myaxi.boundary_size - 4)
+            body(size, offset)
+            print('# iter %d end' % i)
+
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+        vthread.finish()
+
+    def body(size, offset):
+        # write
+        for i in range(size):
+            wdata = i + 100
+            myram.write(i, wdata)
+
+        laddr = 0
+        gaddr = offset
+        myaxi.dma_write(myram, laddr, gaddr, size, port=0)
+        print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
+
+        # write
+        for i in range(size):
+            wdata = i + 1000
+            myram.write(i, wdata)
+
+        laddr = 0
+        gaddr = (size + size) * 4 + offset
+        myaxi.dma_write(myram, laddr, gaddr, size, port=1)
+        print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
+
+        # read
+        laddr = 0
+        gaddr = offset
+        myaxi.dma_read(myram, laddr, gaddr, size, port=1)
+        print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
+
+        for i in range(size):
+            rdata = myram.read(i)
+            if vthread.verilog.NotEql(rdata, i + 100):
+                print('rdata[%d] = %d' % (i, rdata))
+                all_ok.value = False
+
+        # read
+        laddr = 0
+        gaddr = (size + size) * 4 + offset
+        myaxi.dma_read(myram, laddr, gaddr, size, port=0)
+        print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
+
+        for i in range(size):
+            rdata = myram.read(i)
+            if vthread.verilog.NotEql(rdata, i + 1000):
+                print('rdata[%d] = %d' % (i, rdata))
+                all_ok.value = False
+
+    th = vthread.Thread(m, 'th_blink', clk, rst, blink)
+    fsm = th.start(16)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+
+    # active low reset
+    rst_x = ports['RST_X']
+
+    # active low -> active high
+    rst = m.Wire('RST')
+    rst.assign(Not(rst_x))
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst_x, m.make_reset(), period=100, polarity='low')
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)
diff --git a/veriloggen/simulation/simulation.py b/veriloggen/simulation/simulation.py
@@ -68,7 +68,8 @@ def setup_clock(m, clk, hperiod=5):
 
 def setup_reset(m, reset, *statement, **kwargs):
     period = kwargs['period'] if 'period' in kwargs else 100
-    positive = kwargs['positive'] if 'positive' in kwargs else True
+    polarity = kwargs['polarity'] if 'polarity' in kwargs else 'high'
+    positive = 'high' in polarity.lower()
 
     ret = m.Initial(
         reset(not positive),
