new example: chatter_clear

shtaxxx · shtaxxx · commit af85b9e1f85f · 2016-02-09T16:08:03.000+09:00
diff --git a/examples/chatter_clear/Makefile b/examples/chatter_clear/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
diff --git a/examples/chatter_clear/chatter_clear.py b/examples/chatter_clear/chatter_clear.py
@@ -0,0 +1,122 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import os
+import sys
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
+
+from veriloggen import *
+
+def mkChatterClear(length=1024):
+    m = Module("chatter_clear")
+
+    _length = m.Parameter('length', length)
+    
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    din = m.Input('din')
+    dout = m.OutputReg('dout', initval=0)
+
+    seq = Seq(m, 'seq', clk, rst)
+
+    count = m.TmpReg(32)
+    
+    seq.add( count(0), cond=din==dout )
+    seq.add( count.inc(), cond=din!=dout )
+    seq.add( count(0), cond=count==_length )
+    seq.add( dout(din), cond=count==_length )
+
+    seq.make_always()
+
+    return m
+
+def mkTest(length=1024):
+    m = Module('test')
+    
+    main = mkChatterClear(length)
+    params = m.copy_params(main)
+    ports = m.copy_sim_ports(main)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+    din = ports['din']
+    dout = ports['dout']
+
+    fsm = FSM(m, 'fsm', clk, rst)
+    count = m.TmpReg(32, initval=0)
+
+    fsm.add( din(0) )
+    fsm.add( count.inc() )
+    fsm.add( count(0), cond=count==2000 )
+    fsm.goto_next(count==2000)
+
+    fsm.add( din(1) )
+    fsm.add( count.inc() )
+    fsm.add( count(0), cond=count==10 )
+    fsm.goto_next(count==10)
+
+    fsm.add( din(0) )
+    fsm.add( count.inc() )
+    fsm.add( count(0), cond=count==10 )
+    fsm.goto_next(count==10)
+
+    fsm.add( din(1) )
+    fsm.add( count.inc() )
+    fsm.add( count(0), cond=count==2000 )
+    fsm.goto_next(count==2000)
+
+    fsm.add( din(0) )
+    fsm.add( count.inc() )
+    fsm.add( count(0), cond=count==10 )
+    fsm.goto_next(count==10)
+
+    fsm.add( din(1) )
+    fsm.add( count.inc() )
+    fsm.add( count(0), cond=count==10 )
+    fsm.goto_next(count==10)
+
+    fsm.add( din(0) )
+    fsm.add( count.inc() )
+    fsm.add( count(0), cond=count==2000 )
+    fsm.goto_next(count==2000)
+
+    fsm.make_always()
+    
+    uut = m.Instance(main, 'uut',
+                     params=m.connect_params(main),
+                     ports=m.connect_ports(main))
+
+    simulation.setup_waveform(m, uut, m.get_vars())
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    nclk = simulation.next_clock
+    
+    init.add(
+        Delay(1000 * 100),
+        Systask('finish'),
+    )
+
+    return m
+
+if __name__ == '__main__':
+    #main = mkChatterClear()
+    #verilog = main.to_verilog('tmp.v')
+    #print(verilog)
+    #exit()
+    
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)
+
+    # run simulator (Icarus Verilog)
+    sim = simulation.Simulator(test)
+    rslt = sim.run() # display=False
+    #rslt = sim.run(display=True)
+    print(rslt)
+
+    # launch waveform viewer (GTKwave)
+    #sim.view_waveform() # background=False
+    #sim.view_waveform(background=True)
diff --git a/examples/chatter_clear/test_chatter_clear.py b/examples/chatter_clear/test_chatter_clear.py
@@ -0,0 +1,198 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import chatter_clear
+
+expected_verilog = """
+module test #
+(
+  parameter length = 1024
+);
+
+  reg CLK;
+  reg RST;
+  reg din;
+  wire dout;
+  reg [32-1:0] fsm;
+  localparam fsm_init = 0;
+  reg [32-1:0] _tmp_0;
+  localparam fsm_1 = 1;
+  localparam fsm_2 = 2;
+  localparam fsm_3 = 3;
+  localparam fsm_4 = 4;
+  localparam fsm_5 = 5;
+  localparam fsm_6 = 6;
+  localparam fsm_7 = 7;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      fsm <= fsm_init;
+      _tmp_0 <= 0;
+    end else begin
+      case(fsm)
+        fsm_init: begin
+          din <= 0;
+          _tmp_0 <= _tmp_0 + 1;
+          if(_tmp_0 == 2000) begin
+            _tmp_0 <= 0;
+          end 
+          if(_tmp_0 == 2000) begin
+            fsm <= fsm_1;
+          end 
+        end
+        fsm_1: begin
+          din <= 1;
+          _tmp_0 <= _tmp_0 + 1;
+          if(_tmp_0 == 10) begin
+            _tmp_0 <= 0;
+          end 
+          if(_tmp_0 == 10) begin
+            fsm <= fsm_2;
+          end 
+        end
+        fsm_2: begin
+          din <= 0;
+          _tmp_0 <= _tmp_0 + 1;
+          if(_tmp_0 == 10) begin
+            _tmp_0 <= 0;
+          end 
+          if(_tmp_0 == 10) begin
+            fsm <= fsm_3;
+          end 
+        end
+        fsm_3: begin
+          din <= 1;
+          _tmp_0 <= _tmp_0 + 1;
+          if(_tmp_0 == 2000) begin
+            _tmp_0 <= 0;
+          end 
+          if(_tmp_0 == 2000) begin
+            fsm <= fsm_4;
+          end 
+        end
+        fsm_4: begin
+          din <= 0;
+          _tmp_0 <= _tmp_0 + 1;
+          if(_tmp_0 == 10) begin
+            _tmp_0 <= 0;
+          end 
+          if(_tmp_0 == 10) begin
+            fsm <= fsm_5;
+          end 
+        end
+        fsm_5: begin
+          din <= 1;
+          _tmp_0 <= _tmp_0 + 1;
+          if(_tmp_0 == 10) begin
+            _tmp_0 <= 0;
+          end 
+          if(_tmp_0 == 10) begin
+            fsm <= fsm_6;
+          end 
+        end
+        fsm_6: begin
+          din <= 0;
+          _tmp_0 <= _tmp_0 + 1;
+          if(_tmp_0 == 2000) begin
+            _tmp_0 <= 0;
+          end 
+          if(_tmp_0 == 2000) begin
+            fsm <= fsm_7;
+          end 
+        end
+      endcase
+    end
+  end
+
+
+  chatter_clear
+  #(
+    .length(length)
+  )
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .din(din),
+    .dout(dout)
+  );
+
+
+  initial begin
+    $dumpfile("uut.vcd");
+    $dumpvars(0, uut, CLK, RST, din, dout, fsm, _tmp_0);
+  end
+
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = !CLK;
+    end
+  end
+
+
+  initial begin
+    RST = 0;
+    fsm = fsm_init;
+    _tmp_0 = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #100000;
+    $finish;
+  end
+
+
+endmodule
+
+
+
+module chatter_clear #
+(
+  parameter length = 1024
+)
+(
+  input CLK,
+  input RST,
+  input din,
+  output reg dout
+);
+
+  reg [32-1:0] _tmp_0;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      dout <= 0;
+    end else begin
+      if(din == dout) begin
+        _tmp_0 <= 0;
+      end 
+      if(din != dout) begin
+        _tmp_0 <= _tmp_0 + 1;
+      end 
+      if(_tmp_0 == length) begin
+        _tmp_0 <= 0;
+      end 
+      if(_tmp_0 == length) begin
+        dout <= din;
+      end 
+    end
+  end
+
+
+endmodule
+"""
+
+def test():
+    test_module = chatter_clear.mkTest()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)
