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Method hooking for nested modules is supported. Some examples are added.
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‎examples/seq_example/test_seq_example.py‎

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import seq_example
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from veriloggen import *
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expected_verilog = """
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module test #

‎tests/lib_fsm_/hook/lib_fsm_hook.py‎

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fsm.goto(init)
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#fsm.make_always()
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# make_alway() is called when to_veirlog() is called.
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m.add_hook(fsm.make_always, args=(), kwargs={})
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return m
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if __name__ == '__main__':
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led = mkLed()
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# to_verilog() method is immuatable.
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# Hooked methods are called for the copied object to keep the internal state.
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dummy = led.to_verilog()
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verilog = led.to_verilog()
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print(verilog)

‎tests/lib_fsm_/hook/test_lib_fsm_hook.py‎

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def test():
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test_module = lib_fsm_hook.mkLed()
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dummy = test_module.to_verilog()
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code = test_module.to_verilog()
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from pyverilog.vparser.parser import VerilogParser

‎tests/lib_fsm_/hook_nested/Makefile‎

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TARGET=*.py
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

‎tests/lib_fsm_/hook_nested/lib_fsm_hook_nested.py‎

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import sys
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import os
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
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from veriloggen import *
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def mkLed():
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m = Module('blinkled')
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width = m.Parameter('WIDTH', 8)
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clk = m.Input('CLK')
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rst = m.Input('RST')
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led = m.OutputReg('LED', width, initval=0)
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count = m.Reg('count', 32, initval=0)
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"""
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led = 0
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while True:
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count = 0
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while count < 1024:
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count += 1
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led += 1
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"""
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fsm = lib.FSM(m, 'fsm', clk, rst)
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fsm.add( led(0) )
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fsm.goto_next()
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init = fsm.current()
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fsm.add( count(0) )
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fsm.goto_next()
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head = fsm.current()
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cond = count < 1024
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fsm.goto_next(cond=cond)
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fsm.add( count.inc() )
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fsm.goto_next()
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fsm.add( count.inc() )
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fsm.goto(head)
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fsm.inc()
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tail = fsm.current()
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fsm.goto_from(head, tail, cond=Not(cond))
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fsm.add( led.inc() )
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fsm.goto(init)
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#fsm.make_always()
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# make_alway() is called when to_veirlog() is called.
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m.add_hook(fsm.make_always, args=(), kwargs={})
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return m
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def mkTop():
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m = Module('top')
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led = mkLed()
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params = m.copy_params(led)
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ports = m.copy_ports(led)
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m.Instance(led, 'inst_' + led.name,
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connect_same_name(*params.values()),
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connect_same_name(*ports.values()))
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return m
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if __name__ == '__main__':
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top = mkTop()
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# to_verilog() method is immuatable.
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# Hooked methods are called for the copied object to keep the internal state.
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dummy = top.to_verilog()
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verilog = top.to_verilog()
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print(verilog)

‎tests/lib_fsm_/hook_nested/test_lib_fsm_hook_nested.py‎

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import lib_fsm_hook_nested
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expected_verilog = """
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module top #
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(
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parameter WIDTH = 8
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)
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(
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input CLK,
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input RST,
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output [WIDTH-1:0] LED
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);
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blinkled
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#(
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.WIDTH(WIDTH)
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)
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inst_blinkled
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(
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.CLK(CLK),
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.RST(RST),
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.LED(LED)
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);
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endmodule
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module blinkled #
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(
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parameter WIDTH = 8
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)
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(
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input CLK,
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input RST,
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output reg [WIDTH-1:0] LED
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);
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reg [32-1:0] count;
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reg [32-1:0] fsm;
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localparam fsm_init = 0;
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localparam fsm_1 = 1;
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localparam fsm_2 = 2;
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localparam fsm_3 = 3;
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localparam fsm_4 = 4;
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localparam fsm_5 = 5;
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always @(posedge CLK) begin
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if(RST) begin
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fsm <= fsm_init;
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LED <= 0;
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count <= 0;
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end else begin
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case(fsm)
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fsm_init: begin
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LED <= 0;
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fsm <= fsm_1;
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end
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fsm_1: begin
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count <= 0;
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fsm <= fsm_2;
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end
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fsm_2: begin
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if(count < 1024) begin
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fsm <= fsm_3;
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end
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if(!(count < 1024)) begin
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fsm <= fsm_5;
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end
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end
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fsm_3: begin
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count <= count + 1;
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fsm <= fsm_4;
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end
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fsm_4: begin
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count <= count + 1;
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fsm <= fsm_2;
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end
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fsm_5: begin
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LED <= LED + 1;
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fsm <= fsm_1;
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end
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endcase
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end
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end
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endmodule
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"""
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def test():
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test_module = lib_fsm_hook_nested.mkTop()
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dummy = test_module.to_verilog()
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code = test_module.to_verilog()
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from pyverilog.vparser.parser import VerilogParser
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
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parser = VerilogParser()
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expected_ast = parser.parse(expected_verilog)
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codegen = ASTCodeGenerator()
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expected_code = codegen.visit(expected_ast)
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assert(expected_code == code)

‎tests/lib_seq_/basic/Makefile‎

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TARGET=*.py
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

‎tests/lib_seq_/basic/lib_seq_basic.py‎

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import sys
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import os
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
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from veriloggen import *
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def mkLed():
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m = Module('blinkled')
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interval = m.Parameter('INTERVAL', 16)
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clk = m.Input('CLK')
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rst = m.Input('RST')
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led = m.OutputReg('LED', 8, initval=0)
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count = m.Reg('count', 32, initval=0)
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seq = lib.Seq(m, 'seq', clk, rst)
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seq.add( Systask('display', 'LED:%d count:%d', led, count) )
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seq.add( count(count + 1), cond=count<interval-1 )
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seq.add( count(0), cond=count==interval-1 )
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seq.add( led(led + 1), cond=count==interval-1 )
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seq.make_always()
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return m
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def mkTest():
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m = Module('test')
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# target instance
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led = mkLed()
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# copy paras and ports
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params = m.copy_params(led)
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ports = m.copy_sim_ports(led)
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clk = ports['CLK']
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rst = ports['RST']
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uut = m.Instance(led, 'uut',
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params=m.connect_params(led),
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ports=m.connect_ports(led))
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#lib.simulation.setup_waveform(m, uut)
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lib.simulation.setup_clock(m, clk, hperiod=5)
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init = lib.simulation.setup_reset(m, rst, m.make_reset(), period=100)
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init.add(
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Delay(1000),
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Systask('finish'),
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)
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return m
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if __name__ == '__main__':
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test = mkTest()
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verilog = test.to_verilog()
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print(verilog)

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