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dataflow -> pipeline
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+78
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File renamed without changes.

examples/dataflow_example/dataflow_example.py renamed to examples/pipeline_example/pipeline_example.py

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -31,28 +31,28 @@ def mkMultAdd():
3131
vz = m.Output('vz')
3232
rz = m.Input('rz')
3333

34-
# dataflow manager
35-
df = Dataflow(m, 'df', clk, rst)
34+
# pipeline manager
35+
df = Pipeline(m, 'df', clk, rst)
3636

37-
# input -> dataflow variable
37+
# input -> pipeline variable
3838
px = df.input(x, valid=vx, ready=rx)
3939
py = df.input(y, valid=vy, ready=ry)
4040

41-
# dataflow definitions
41+
# pipeline definitions
4242
pxc = df(px * c)
4343
pz = df(pxc + py)
4444

45-
# dataflow variable -> output
45+
# pipeline variable -> output
4646
pz.output(z, valid=vz, ready=rz)
4747

4848
# generate always statement
4949
df.make_always()
5050

51-
# draw dataflow graph in png
51+
# draw pipeline graph in png
5252
try:
5353
df.draw_graph()
5454
except:
55-
print('Dataflow graph could not be generated.', file=sys.stderr)
55+
print('Pipeline graph could not be generated.', file=sys.stderr)
5656

5757
return m
5858

examples/dataflow_example/test_dataflow_example.py renamed to examples/pipeline_example/test_pipeline_example.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
from __future__ import absolute_import
22
from __future__ import print_function
3-
import dataflow_example
3+
import pipeline_example
44
from veriloggen import *
55

66
expected_verilog = """
@@ -349,7 +349,7 @@
349349
"""
350350

351351
def test():
352-
test_module = dataflow_example.mkTest()
352+
test_module = pipeline_example.mkTest()
353353
code = test_module.to_verilog()
354354

355355
from pyverilog.vparser.parser import VerilogParser
File renamed without changes.

examples/dataflow_multiple_add/dataflow_multiple_add.py renamed to examples/pipeline_multiple_add/pipeline_multiple_add.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ def mkAdd(numports=8, mode=1):
2121
vz = m.Output('vz')
2222
rz = m.Input('rz')
2323

24-
df = Dataflow(m, 'df', clk, rst)
24+
df = Pipeline(m, 'df', clk, rst)
2525

2626
dfvars = [ df.input(*p) for p in inputs ]
2727

@@ -48,7 +48,7 @@ def mkAdd(numports=8, mode=1):
4848
try:
4949
df.draw_graph()
5050
except:
51-
print('Dataflow graph could not be generated.', file=sys.stderr)
51+
print('Pipeline graph could not be generated.', file=sys.stderr)
5252

5353
return m
5454

examples/dataflow_multiple_add/test_dataflow_multiple_add.py renamed to examples/pipeline_multiple_add/test_pipeline_multiple_add.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
from __future__ import absolute_import
22
from __future__ import print_function
3-
import dataflow_multiple_add
3+
import pipeline_multiple_add
44
from veriloggen import *
55

66
expected_verilog = """
@@ -1024,7 +1024,7 @@
10241024
"""
10251025

10261026
def test():
1027-
test_module = dataflow_multiple_add.mkTest()
1027+
test_module = pipeline_multiple_add.mkTest()
10281028
code = test_module.to_verilog()
10291029

10301030
from pyverilog.vparser.parser import VerilogParser
File renamed without changes.

tests/extension/dataflow_/acc_add/dataflow_acc_add.py renamed to tests/extension/pipeline_/acc_add/pipeline_acc_add.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ def mkLed():
1616
y = m.Output('y', 32)
1717
prst = m.Input('prst')
1818

19-
df = Dataflow(m, 'df', clk, rst)
19+
df = Pipeline(m, 'df', clk, rst)
2020

2121
px = df.input(x)
2222
psum = df.acc_add(px, initval=0, resetcond=prst)

tests/extension/dataflow_/acc_add/test_dataflow_acc_add.py renamed to tests/extension/pipeline_/acc_add/test_pipeline_acc_add.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
from __future__ import absolute_import
22
from __future__ import print_function
3-
import dataflow_acc_add
3+
import pipeline_acc_add
44

55
expected_verilog = """
66
module test;
@@ -142,7 +142,7 @@
142142
"""
143143

144144
def test():
145-
test_module = dataflow_acc_add.mkTest()
145+
test_module = pipeline_acc_add.mkTest()
146146
code = test_module.to_verilog()
147147

148148
from pyverilog.vparser.parser import VerilogParser

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