vtypes.Int is updated: Int, IntX, IntZ are merged.

Author: shtaxxx

tests/_int/Makefile

@@ -0,0 +1,29 @@
+TARGET=*.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

tests/_int/_int.py

@@ -0,0 +1,72 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + Int(1))
+            )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(0)
+        ).Else(
+            If(count == 1024 - 1)(
+                led(Int("'h10"))
+            )
+        ))
+
+    return m
+
+def mkTest():
+    m = Module('test')
+    
+    # target instance
+    led = mkLed()
+    
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+    
+    clk = ports['CLK']
+    rst = ports['RST']
+    
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+    
+    lib.simulation.setup_waveform(m, uut, m.get_vars())
+    lib.simulation.setup_clock(m, clk, hperiod=5)
+    init = lib.simulation.setup_reset(m, rst, m.make_reset(), period=100)
+    
+    init.add(
+        Delay(1000 * 100),
+        Systask('finish'),
+    )
+
+    return m
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)

tests/_int/test__int.py

@@ -0,0 +1,95 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import _int
+
+expected_verilog = """
+module test #
+(
+  parameter WIDTH = 8
+)
+(
+);
+
+  reg CLK;
+  reg RST;
+  wire [(WIDTH - 1):0] LED;
+
+  blinkled
+  #(
+    .WIDTH(WIDTH)
+  )
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .LED(LED)
+  );
+
+  initial begin
+    $dumpfile("uut.vcd");
+    $dumpvars(0, uut, CLK, RST, LED);
+  end
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = (!CLK);
+    end
+  end
+
+  initial begin
+    RST = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #100000;
+    $finish;
+  end
+endmodule
+
+module blinkled #
+  ( 
+   parameter WIDTH = 8
+  )
+  ( 
+   input CLK, 
+   input RST,
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      if(count == 1023) begin
+        count <= 0;
+      end else begin
+        count <= count + 1;
+      end
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin
+        LED <= 'h10;
+      end 
+    end
+  end
+endmodule
+"""
+
+def test():
+    test_module = _int.mkTest()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

tests/intx/test_intx.py

@@ -74,7 +74,7 @@
       LED <= 0;
     end else begin
       if(count == 1023) begin
-        LED <= 'dx;
+        LED <= 'hx;
       end 
     end
   end

tests/intz/test_intz.py

@@ -74,7 +74,7 @@
       LED <= 0;
     end else begin
       if(count == 1023) begin
-        LED <= 'dz;
+        LED <= 'hz;
       end 
     end
   end

veriloggen/from_verilog.py

@@ -81,45 +81,6 @@ def to_ast(*filelist, **opt):
     return ast
 
 #-------------------------------------------------------------------------------
-def str_to_signed(s):
-    targ = s.replace('_','')
-    match = re.search(r's(.+)', targ)
-    if match is not None:
-        return True
-    return False
-
-def str_to_value(s):
-    targ = s.replace('_','')
-    match = re.search(r'h(.+)', targ)
-    if match is not None:
-        return int(match.group(1), 16), 16
-    match = re.search(r'd(.+)', targ)
-    if match is not None:
-        return int(match.group(1), 10), 10
-    match = re.search(r'o(.+)', targ)
-    if match is not None:
-        return int(match.group(1), 8), 8
-    match = re.search(r'b(.+)', targ)
-    if match is not None:
-        return int(match.group(1), 2), 2
-    return int(targ, 10), None
-        
-def str_to_width(s):
-    targ = s.replace('_','')
-    match = re.search(r'(.+)\'h.+', targ)
-    if match is not None:
-        return int(match.group(1), 10)
-    match = re.search(r'(.+)\'d.+', targ)
-    if match is not None:
-        return int(match.group(1), 10)
-    match = re.search(r'(.+)\'o.+', targ)
-    if match is not None:
-        return int(match.group(1), 10)
-    match = re.search(r'(.+)\'b.+', targ)
-    if match is not None:
-        return int(match.group(1), 10)
-    return None
-
 def to_tuple(s):
     if not isinstance(s, (list, tuple)):
         return tuple([s])
@@ -205,9 +166,9 @@ def visit_Identifier(self, node):
         return self.m.find_identifier(node.name)
 
     def visit_IntConst(self, node):
-        value, base = str_to_value(node.value)
-        width = str_to_width(node.value)
-        signed = str_to_signed(node.value)
+        value, base = vtypes.str_to_value(node.value)
+        width = vtypes.str_to_width(node.value)
+        signed = vtypes.str_to_signed(node.value)
         return vtypes.Int(value, width, base, signed)
 
     def visit_FloatConst(self, node):