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1 parent 1d2a5c8 commit ca67166Copy full SHA for ca67166
veriloggen/to_verilog.py
@@ -466,7 +466,8 @@ def make_length(self, node):
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#---------------------------------------------------------------------------
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def visit(self, node):
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- if isinstance(node, module.Module): return self.visit_Module(node)
+ if isinstance(node, module.Module) and not isinstance(node, module.Generate):
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+ return self.visit_Module(node)
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visitor = getattr(self, 'visit_' + node.__class__.__name__, self.generic_visit)
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return visitor(node)
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