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lib_simulation_simulator is added: executing a simulation of Veriloggen hardware module on Python with Icarus.
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‎tests/lib_simulation_/simulator/Makefile‎

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TARGET=*.py
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd

‎tests/lib_simulation_/simulator/lib_simulation_simulator.py‎

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import sys
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import os
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
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from veriloggen import *
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def mkLed():
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m = Module('blinkled')
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width = m.Parameter('WIDTH', 8)
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clk = m.Input('CLK')
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rst = m.Input('RST')
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led = m.OutputReg('LED', width)
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count = m.Reg('count', 32)
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m.Always(Posedge(clk))(
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If(rst)(
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count(0)
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).Else(
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If(count == 16 - 1)(
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count(0)
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).Else(
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count(count + 1)
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)
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))
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m.Always(Posedge(clk))(
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If(rst)(
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led(0)
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).Else(
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Systask('display', 'LED:%d count:%d', led, count),
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If(count == 16 - 1)(
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led(led + 1)
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)
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))
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return m
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def mkTest():
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m = Module('test')
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width = m.Parameter('WIDTH', 8)
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clk = m.Reg('CLK')
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rst = m.Reg('RST')
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led = m.Wire('LED', width)
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uut = m.Instance(mkLed(), 'uut',
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params=connect_same_name(width),
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ports=connect_same_name(clk, rst, led))
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lib.simulation.setup_waveform(m, uut)
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lib.simulation.setup_clock(m, clk, hperiod=5)
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init = lib.simulation.setup_reset(m, rst, period=100)
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init.add(
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Delay(1000),
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Systask('finish'),
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)
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return m
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if __name__ == '__main__':
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test = mkTest()
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verilog = test.to_verilog()
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print(verilog)
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sim = lib.simulation.Simulator(test)
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rslt = sim.run()
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print(rslt)

‎tests/lib_simulation_/simulator/test_lib_simulation_simulator.py‎

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import lib_simulation_simulator
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from veriloggen import *
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expected_verilog = """
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module test #
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(
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parameter WIDTH = 8
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)
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(
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);
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reg CLK;
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reg RST;
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wire [WIDTH-1:0] LED;
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blinkled #
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(
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.WIDTH(WIDTH)
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)
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uut
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(
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.CLK(CLK),
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.RST(RST),
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.LED(LED)
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);
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initial begin
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$dumpfile("uut.vcd");
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$dumpvars(0, uut);
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end
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initial begin
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CLK = 0;
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forever begin
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#5 CLK = !CLK;
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end
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end
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initial begin
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RST = 0;
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#100;
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RST = 1;
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#100;
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RST = 0;
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#1000;
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$finish;
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end
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endmodule
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module blinkled #
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(
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parameter WIDTH = 8
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)
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(
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input CLK,
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input RST,
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output reg [WIDTH-1:0] LED
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);
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reg [32-1:0] count;
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always @(posedge CLK) begin
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if(RST) begin
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count <= 0;
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end else begin
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if(count == 15) begin
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count <= 0;
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end else begin
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count <= count + 1;
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end
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end
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end
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always @(posedge CLK) begin
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if(RST) begin
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LED <= 0;
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end else begin
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$display("LED:%d count:%d", LED, count);
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if(count == 15) begin
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LED <= LED + 1;
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end
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end
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end
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endmodule
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"""
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expected_rslt = """\
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VCD info: dumpfile uut.vcd opened for output.
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LED: x count: x
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LED: x count: x
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LED: x count: x
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LED: x count: x
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LED: x count: x
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LED: x count: x
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LED: x count: x
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LED: x count: x
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LED: x count: x
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LED: x count: x
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LED: 0 count: 0
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LED: 0 count: 1
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LED: 0 count: 2
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LED: 0 count: 3
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LED: 0 count: 4
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LED: 0 count: 5
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LED: 0 count: 6
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LED: 0 count: 7
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LED: 0 count: 8
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LED: 0 count: 9
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LED: 0 count: 10
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LED: 0 count: 11
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LED: 0 count: 12
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LED: 0 count: 13
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LED: 0 count: 14
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LED: 0 count: 15
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LED: 1 count: 0
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LED: 1 count: 1
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LED: 1 count: 2
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LED: 1 count: 3
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LED: 1 count: 4
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LED: 1 count: 5
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LED: 1 count: 6
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LED: 1 count: 7
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LED: 1 count: 8
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LED: 1 count: 9
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LED: 1 count: 10
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LED: 1 count: 11
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LED: 1 count: 12
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LED: 1 count: 13
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LED: 1 count: 14
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LED: 1 count: 15
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LED: 2 count: 0
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LED: 2 count: 1
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LED: 2 count: 2
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LED: 2 count: 3
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LED: 2 count: 4
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LED: 2 count: 5
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LED: 2 count: 6
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LED: 2 count: 7
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LED: 2 count: 8
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LED: 2 count: 9
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LED: 2 count: 10
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LED: 2 count: 11
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LED: 2 count: 12
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LED: 2 count: 13
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LED: 2 count: 14
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LED: 2 count: 15
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LED: 3 count: 0
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LED: 3 count: 1
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LED: 3 count: 2
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LED: 3 count: 3
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LED: 3 count: 4
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LED: 3 count: 5
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LED: 3 count: 6
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LED: 3 count: 7
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LED: 3 count: 8
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LED: 3 count: 9
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LED: 3 count: 10
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LED: 3 count: 11
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LED: 3 count: 12
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LED: 3 count: 13
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LED: 3 count: 14
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LED: 3 count: 15
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LED: 4 count: 0
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LED: 4 count: 1
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LED: 4 count: 2
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LED: 4 count: 3
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LED: 4 count: 4
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LED: 4 count: 5
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LED: 4 count: 6
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LED: 4 count: 7
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LED: 4 count: 8
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LED: 4 count: 9
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LED: 4 count: 10
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LED: 4 count: 11
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LED: 4 count: 12
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LED: 4 count: 13
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LED: 4 count: 14
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LED: 4 count: 15
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LED: 5 count: 0
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LED: 5 count: 1
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LED: 5 count: 2
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LED: 5 count: 3
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LED: 5 count: 4
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LED: 5 count: 5
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LED: 5 count: 6
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LED: 5 count: 7
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LED: 5 count: 8
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LED: 5 count: 9
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LED: 5 count: 10
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LED: 5 count: 11
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LED: 5 count: 12
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LED: 5 count: 13
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LED: 5 count: 14
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LED: 5 count: 15
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LED: 6 count: 0
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LED: 6 count: 1
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LED: 6 count: 2
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LED: 6 count: 3
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"""
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def test():
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test_module = lib_simulation_simulator.mkTest()
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code = test_module.to_verilog()
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from pyverilog.vparser.parser import VerilogParser
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
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parser = VerilogParser()
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expected_ast = parser.parse(expected_verilog)
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codegen = ASTCodeGenerator()
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expected_code = codegen.visit(expected_ast)
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assert(expected_code == code)
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sim = lib.simulation.Simulator(test_module)
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rslt = sim.run()
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assert(expected_rslt == rslt)

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