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First examples are updated.
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-61
lines changed

4 files changed

+10149
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lines changed

README.md

Lines changed: 14 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,7 @@ import sys
134134
import os
135135
from veriloggen import *
136136

137+
137138
def mkLed():
138139
m = Module('blinkled')
139140
width = m.Parameter('WIDTH', 8)
@@ -152,7 +153,7 @@ def mkLed():
152153
count(count + 1)
153154
)
154155
))
155-
156+
156157
m.Always(Posedge(clk))(
157158
If(rst)(
158159
led(0)
@@ -161,43 +162,37 @@ def mkLed():
161162
led(led + 1)
162163
)
163164
))
164-
165+
165166
m.Always(Posedge(clk))(
166167
If(rst)(
167168
).Else(
168169
Systask('display', "LED:%d count:%d", led, count)
169170
))
170-
171+
171172
return m
172173

174+
173175
def mkTest():
174176
m = Module('test')
175-
177+
176178
# target instance
177179
led = mkLed()
178-
179-
# copy paras and ports
180-
params = m.copy_params(led)
181-
ports = m.copy_sim_ports(led)
182-
183-
clk = ports['CLK']
184-
rst = ports['RST']
185-
186-
uut = m.Instance(led, 'uut',
187-
params=m.connect_params(led),
188-
ports=m.connect_ports(led))
189-
180+
181+
uut = Submodule(m, led, name='uut')
182+
clk = uut['CLK']
183+
rst = uut['RST']
184+
190185
simulation.setup_waveform(m, uut, m.get_vars())
191186
simulation.setup_clock(m, clk, hperiod=5)
192187
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
193-
188+
194189
init.add(
195190
Delay(1000 * 100),
196191
Systask('finish'),
197192
)
198193

199194
return m
200-
195+
201196
if __name__ == '__main__':
202197
test = mkTest()
203198
verilog = test.to_verilog(filename='tmp.v')
@@ -208,7 +203,7 @@ if __name__ == '__main__':
208203
rslt = sim.run()
209204
print(rslt)
210205

211-
#sim.view_waveform()
206+
# sim.view_waveform()
212207
```
213208

214209
Run the script.

README.rst

Lines changed: 14 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -156,6 +156,7 @@ Python as below. A blinking LED hardware is modeled in Python. Open
156156
import os
157157
from veriloggen import *
158158
159+
159160
def mkLed():
160161
m = Module('blinkled')
161162
width = m.Parameter('WIDTH', 8)
@@ -174,7 +175,7 @@ Python as below. A blinking LED hardware is modeled in Python. Open
174175
count(count + 1)
175176
)
176177
))
177-
178+
178179
m.Always(Posedge(clk))(
179180
If(rst)(
180181
led(0)
@@ -183,43 +184,37 @@ Python as below. A blinking LED hardware is modeled in Python. Open
183184
led(led + 1)
184185
)
185186
))
186-
187+
187188
m.Always(Posedge(clk))(
188189
If(rst)(
189190
).Else(
190191
Systask('display', "LED:%d count:%d", led, count)
191192
))
192-
193+
193194
return m
194195
196+
195197
def mkTest():
196198
m = Module('test')
197-
199+
198200
# target instance
199201
led = mkLed()
200-
201-
# copy paras and ports
202-
params = m.copy_params(led)
203-
ports = m.copy_sim_ports(led)
204-
205-
clk = ports['CLK']
206-
rst = ports['RST']
207-
208-
uut = m.Instance(led, 'uut',
209-
params=m.connect_params(led),
210-
ports=m.connect_ports(led))
211-
202+
203+
uut = Submodule(m, led, name='uut')
204+
clk = uut['CLK']
205+
rst = uut['RST']
206+
212207
simulation.setup_waveform(m, uut, m.get_vars())
213208
simulation.setup_clock(m, clk, hperiod=5)
214209
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
215-
210+
216211
init.add(
217212
Delay(1000 * 100),
218213
Systask('finish'),
219214
)
220215
221216
return m
222-
217+
223218
if __name__ == '__main__':
224219
test = mkTest()
225220
verilog = test.to_verilog(filename='tmp.v')
@@ -230,7 +225,7 @@ Python as below. A blinking LED hardware is modeled in Python. Open
230225
rslt = sim.run()
231226
print(rslt)
232227
233-
#sim.view_waveform()
228+
# sim.view_waveform()
234229
235230
Run the script.
236231

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