A bug fix for Async stream execution via source_join()

Author: shtaxxx

tests/extension/stream_/reduceadd/test_stream_reduceadd.py

@@ -194,19 +194,19 @@
         _reduceadd_data_6 <= _reduceadd_data_6 + _plus_data_3;
       end 
       if(__delay_data_10) begin
-        _reduceadd_count_6 <= (_reduceadd_count_6 == 5'sd8 - 1)? 0 : _reduceadd_count_6 + 1;
+        _reduceadd_count_6 <= (_reduceadd_count_6 >= 5'sd8 - 1)? 0 : _reduceadd_count_6 + 1;
       end 
       if(__delay_data_10 && (_reduceadd_count_6 == 0)) begin
         _reduceadd_data_6 <= 1'sd0 + _plus_data_3;
       end 
       if(__delay_data_10) begin
-        _pulse_data_9 <= _pulse_count_9 == 5'sd8 - 1;
+        _pulse_data_9 <= _pulse_count_9 >= 5'sd8 - 1;
       end 
       if(__delay_data_10) begin
-        _pulse_count_9 <= (_pulse_count_9 == 5'sd8 - 1)? 0 : _pulse_count_9 + 1;
+        _pulse_count_9 <= (_pulse_count_9 >= 5'sd8 - 1)? 0 : _pulse_count_9 + 1;
       end 
       if(__delay_data_10 && (_pulse_count_9 == 0)) begin
-        _pulse_data_9 <= _pulse_count_9 == 5'sd8 - 1;
+        _pulse_data_9 <= _pulse_count_9 >= 5'sd8 - 1;
       end 
     end
   end

tests/extension/stream_/reduceadd_valid/test_stream_reduceadd_valid.py

@@ -208,19 +208,19 @@
         _reduceadd_data_5 <= _reduceadd_data_5 + _plus_data_2;
       end 
       if(_ivalid_0) begin
-        _reduceadd_count_5 <= (_reduceadd_count_5 == 5'sd8 - 1)? 0 : _reduceadd_count_5 + 1;
+        _reduceadd_count_5 <= (_reduceadd_count_5 >= 5'sd8 - 1)? 0 : _reduceadd_count_5 + 1;
       end 
       if(_ivalid_0 && (_reduceadd_count_5 == 0)) begin
         _reduceadd_data_5 <= 1'sd0 + _plus_data_2;
       end 
       if(_ivalid_0) begin
-        _pulse_data_8 <= _pulse_count_8 == 5'sd8 - 1;
+        _pulse_data_8 <= _pulse_count_8 >= 5'sd8 - 1;
       end 
       if(_ivalid_0) begin
-        _pulse_count_8 <= (_pulse_count_8 == 5'sd8 - 1)? 0 : _pulse_count_8 + 1;
+        _pulse_count_8 <= (_pulse_count_8 >= 5'sd8 - 1)? 0 : _pulse_count_8 + 1;
       end 
       if(_ivalid_0 && (_pulse_count_8 == 0)) begin
-        _pulse_data_8 <= _pulse_count_8 == 5'sd8 - 1;
+        _pulse_data_8 <= _pulse_count_8 >= 5'sd8 - 1;
       end 
     end
   end

tests/extension/stream_/reduceadd_validready/test_stream_reduceadd_validready.py

@@ -237,19 +237,19 @@
         _reduceadd_data_5 <= _reduceadd_data_5 + _plus_data_2;
       end 
       if(_ivalid_0 && _tmp_0) begin
-        _reduceadd_count_5 <= (_reduceadd_count_5 == 5'sd8 - 1)? 0 : _reduceadd_count_5 + 1;
+        _reduceadd_count_5 <= (_reduceadd_count_5 >= 5'sd8 - 1)? 0 : _reduceadd_count_5 + 1;
       end 
       if(_ivalid_0 && _tmp_0 && (_reduceadd_count_5 == 0)) begin
         _reduceadd_data_5 <= 1'sd0 + _plus_data_2;
       end 
       if(_ivalid_0 && _tmp_0) begin
-        _pulse_data_8 <= _pulse_count_8 == 5'sd8 - 1;
+        _pulse_data_8 <= _pulse_count_8 >= 5'sd8 - 1;
       end 
       if(_ivalid_0 && _tmp_0) begin
-        _pulse_count_8 <= (_pulse_count_8 == 5'sd8 - 1)? 0 : _pulse_count_8 + 1;
+        _pulse_count_8 <= (_pulse_count_8 >= 5'sd8 - 1)? 0 : _pulse_count_8 + 1;
       end 
       if(_ivalid_0 && _tmp_0 && (_pulse_count_8 == 0)) begin
-        _pulse_data_8 <= _pulse_count_8 == 5'sd8 - 1;
+        _pulse_data_8 <= _pulse_count_8 >= 5'sd8 - 1;
       end 
     end
   end

tests/extension/stream_/substream/test_stream_substream.py

@@ -269,19 +269,19 @@
         _reduceadd_data_14 <= _reduceadd_data_14 + __substreamoutput_data_11;
       end 
       if(__delay_data_29) begin
-        _reduceadd_count_14 <= (_reduceadd_count_14 == 5'sd8 - 1)? 0 : _reduceadd_count_14 + 1;
+        _reduceadd_count_14 <= (_reduceadd_count_14 >= 5'sd8 - 1)? 0 : _reduceadd_count_14 + 1;
       end 
       if(__delay_data_29 && (_reduceadd_count_14 == 0)) begin
         _reduceadd_data_14 <= 1'sd0 + __substreamoutput_data_11;
       end 
       if(__delay_data_29) begin
-        _pulse_data_17 <= _pulse_count_17 == 5'sd8 - 1;
+        _pulse_data_17 <= _pulse_count_17 >= 5'sd8 - 1;
       end 
       if(__delay_data_29) begin
-        _pulse_count_17 <= (_pulse_count_17 == 5'sd8 - 1)? 0 : _pulse_count_17 + 1;
+        _pulse_count_17 <= (_pulse_count_17 >= 5'sd8 - 1)? 0 : _pulse_count_17 + 1;
       end 
       if(__delay_data_29 && (_pulse_count_17 == 0)) begin
-        _pulse_data_17 <= _pulse_count_17 == 5'sd8 - 1;
+        _pulse_data_17 <= _pulse_count_17 >= 5'sd8 - 1;
       end 
       _plus_data_18 <= _reduceadd_data_14 + 11'sd1000;
       __delay_data_30 <= _pulse_data_17;

tests/extension/thread_/stream_pattern/thread_stream_pattern.py

@@ -70,6 +70,7 @@ def check(size, offset_stream, offset_seq):
             sq = ram_c.read(i + offset_seq)
             if vthread.verilog.NotEql(st, sq):
                 all_ok = False
+                print(i, st, sq)
         if all_ok:
             print('# verify: PASSED')
         else:

tests/extension/thread_/stream_pattern_source_join/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/thread_/stream_pattern_source_join/test_thread_stream_pattern_source_join.py

@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_pattern_source_join
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_pattern_source_join.run(filename=None, simtype=simtype,
+                                                 outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')

tests/extension/thread_/stream_pattern_source_join/thread_stream_pattern_source_join.py

@@ -0,0 +1,156 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+    ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+    a = strm.source('a')
+    b = strm.source('b')
+    c = a * b
+    strm.sink(c, 'c')
+
+    def comp_stream(size, offset):
+        strm.set_source_pattern('a', ram_a, offset, (size, 1))
+        strm.set_source_pattern('b', ram_b, offset, (size, 1))
+        strm.set_sink_pattern('c', ram_c, offset, (size, 1))
+        strm.run()
+
+        # double buffer of comp and cmd
+        strm.set_source_pattern('a', ram_a, offset + size, (size, 1))
+        strm.set_source_pattern('b', ram_b, offset + size, (size, 1))
+        strm.set_sink_pattern('c', ram_c, offset + size, (size, 1))
+        strm.source_join()
+
+        strm.run()
+
+        # double buffer of comp and cmd
+        strm.set_source_pattern('a', ram_a, offset + size + size, (size, 1))
+        strm.set_source_pattern('b', ram_b, offset + size + size, (size, 1))
+        strm.set_sink_pattern('c', ram_c, offset + size + size, (size, 1))
+        strm.source_join()
+
+        strm.run()
+
+        strm.source_join()
+        strm.sink_join()
+
+    def comp_sequential(size, offset):
+        sum = 0
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            b = ram_b.read(i + offset)
+            sum = a * b
+            ram_c.write(i + offset, sum)
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_c.read(i + offset_stream)
+            sq = ram_c.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        new_size = size + size + size
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, new_size)
+        myaxi.dma_read(ram_b, offset, 512, new_size)
+        comp_stream(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024, new_size)
+
+        offset = new_size
+        myaxi.dma_read(ram_a, offset, 0, new_size)
+        myaxi.dma_read(ram_b, offset, 512, new_size)
+        comp_sequential(new_size, offset)
+        myaxi.dma_write(ram_c, offset, 1024 * 2, new_size)
+
+        check(new_size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)

veriloggen/stream/stypes.py

@@ -1897,13 +1897,6 @@ def __init__(self, right, size=None, initval=None,
                  enable=None, reset=None, width=32, signed=True):
 
         self.size = _to_constant(size) if size is not None else None
-
-        if (self.size is not None and
-            not isinstance(self.size, _Constant) and
-                not isinstance(self.size, _ParameterVariable)):
-            raise TypeError("size must be _Constant or _ParameterVariable, not '%s'" %
-                            str(type(self.size)))
-
         self.initval = (_to_constant(initval)
                         if initval is not None else _to_constant(0))
 
@@ -1957,7 +1950,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
         if self.size is not None:
             count = m.Reg(self.name('count'),
                           size_data.bit_length() + 1, initval=0)
-            next_count_value = vtypes.Mux(count == size_data - 1,
+            next_count_value = vtypes.Mux(count >= size_data - 1,
                                           0, count + 1)
             count_zero = (count == 0)
 
@@ -1982,7 +1975,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
 
         # for Pulse
         if not self.ops and self.size is not None:
-            value = (count == (size_data - 1))
+            value = (count >= (size_data - 1))
 
         if self.reset is not None or self.size is not None:
             reset_value = initval_data
@@ -1999,7 +1992,7 @@ def _implement(self, m, seq, svalid=None, senable=None):
                                     % (str(op), str(type(reset_value))))
 
             if not self.ops and self.size is not None:
-                reset_value = (count == (size_data - 1))
+                reset_value = (count >= (size_data - 1))
 
         if self.enable is not None:
             enable_cond = _and_vars(svalid, senable, enabledata)