lib.fsm is updated: make_reset is implemened and Module.make_reset is never used by fsm.

shtaxxx · shtaxxx · commit e3102c0eaea1 · 2015-09-17T08:19:05.000+09:00
diff --git a/sample/tests/lib_fsm/delayed/test_led.py b/sample/tests/lib_fsm/delayed/test_led.py
@@ -61,9 +61,9 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      valid <= 0;
       fsm <= fsm_init;
       _d1_fsm <= fsm_init;
+      valid <= 0;
     end else begin
       _d1_fsm <= fsm;
       case(_d1_fsm)
diff --git a/sample/tests/lib_fsm/delayed_cond/led.py b/sample/tests/lib_fsm/delayed_cond/led.py
@@ -37,7 +37,7 @@ def mkLed():
         fsm.add( valid(0), cond=c, delay=4 )
         fsm.goto_next(cond=c)
 
-    fsm.make_always(clk, rst, body=[count(count+1)])
+    fsm.make_always(clk, rst, reset=[count.reset()], body=[count(count+1)])
         
     return m
 
diff --git a/sample/tests/lib_fsm/delayed_cond/test_led.py b/sample/tests/lib_fsm/delayed_cond/test_led.py
@@ -162,15 +162,16 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      valid <= 0;
       count <= 0;
       fsm <= fsm_init;
       _d1_fsm <= fsm_init;
-      _fsm_cond_4_0_1 <= 0;
       _d2_fsm <= fsm_init;
+      _d3_fsm <= fsm_init;
+      _d4_fsm <= fsm_init;
+      valid <= 0;
+      _fsm_cond_4_0_1 <= 0;
       _fsm_cond_4_1_1 <= 0;
       _fsm_cond_4_1_2 <= 0;
-      _d3_fsm <= fsm_init;
       _fsm_cond_4_2_1 <= 0;
       _fsm_cond_4_2_2 <= 0;
       _fsm_cond_4_2_3 <= 0;
@@ -180,7 +181,6 @@
       _fsm_cond_13_5_1 <= 0;
       _fsm_cond_13_5_2 <= 0;
       _fsm_cond_13_5_3 <= 0;
-      _d4_fsm <= fsm_init;
       _fsm_cond_13_6_1 <= 0;
       _fsm_cond_13_6_2 <= 0;
       _fsm_cond_13_6_3 <= 0;
diff --git a/sample/tests/lib_fsm/delayed_eager_val/led.py b/sample/tests/lib_fsm/delayed_eager_val/led.py
@@ -45,7 +45,7 @@ def mkLed():
         fsm.add( valid_reg(down), cond=c, delay=4, eager_val=True)
         fsm.goto_next(cond=c)
     
-    fsm.make_always(clk, rst, body=[count(count+1)])
+    fsm.make_always(clk, rst, reset=[count.reset()], body=[count(count+1)])
 
     return m
 
diff --git a/sample/tests/lib_fsm/delayed_eager_val/test_led.py b/sample/tests/lib_fsm/delayed_eager_val/test_led.py
@@ -257,17 +257,18 @@
   always @(posedge CLK) begin
     if(RST) begin
       count <= 0;
-      valid_reg <= 0;
       fsm <= fsm_init;
       _d1_fsm <= fsm_init;
+      _d2_fsm <= fsm_init;
+      _d3_fsm <= fsm_init;
+      _d4_fsm <= fsm_init;
+      valid_reg <= 0;
       _valid_reg_4_0_1 <= 0;
       _fsm_cond_4_1_1 <= 0;
-      _d2_fsm <= fsm_init;
       _valid_reg_4_2_1 <= 0;
       _valid_reg_4_2_2 <= 0;
       _fsm_cond_4_3_1 <= 0;
       _fsm_cond_4_3_2 <= 0;
-      _d3_fsm <= fsm_init;
       _valid_reg_4_4_1 <= 0;
       _valid_reg_4_4_2 <= 0;
       _valid_reg_4_4_3 <= 0;
@@ -286,7 +287,6 @@
       _fsm_cond_13_11_1 <= 0;
       _fsm_cond_13_11_2 <= 0;
       _fsm_cond_13_11_3 <= 0;
-      _d4_fsm <= fsm_init;
       _valid_reg_13_12_1 <= 0;
       _valid_reg_13_12_2 <= 0;
       _valid_reg_13_12_3 <= 0;
diff --git a/sample/tests/lib_fsm/delayed_eager_val_lazy_cond/led.py b/sample/tests/lib_fsm/delayed_eager_val_lazy_cond/led.py
@@ -42,7 +42,7 @@ def mkLed():
         fsm.add( valid(down), cond=c, delay=4, eager_val=True, lazy_cond=True)
         fsm.goto_next(cond=c)
     
-    fsm.make_always(clk, rst, body=[count(count+1)])
+    fsm.make_always(clk, rst, reset=[count.reset()], body=[count(count+1)])
 
     return m
 
diff --git a/sample/tests/lib_fsm/delayed_eager_val_lazy_cond/test_led.py b/sample/tests/lib_fsm/delayed_eager_val_lazy_cond/test_led.py
@@ -167,15 +167,16 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      valid <= 0;
       count <= 0;
       fsm <= fsm_init;
       _d1_fsm <= fsm_init;
-      _valid_4_0_1 <= 0;
       _d2_fsm <= fsm_init;
+      _d3_fsm <= fsm_init;
+      _d4_fsm <= fsm_init;
+      valid <= 0;
+      _valid_4_0_1 <= 0;
       _valid_4_1_1 <= 0;
       _valid_4_1_2 <= 0;
-      _d3_fsm <= fsm_init;
       _valid_4_2_1 <= 0;
       _valid_4_2_2 <= 0;
       _valid_4_2_3 <= 0;
@@ -185,7 +186,6 @@
       _valid_13_5_1 <= 0;
       _valid_13_5_2 <= 0;
       _valid_13_5_3 <= 0;
-      _d4_fsm <= fsm_init;
       _valid_13_6_1 <= 0;
       _valid_13_6_2 <= 0;
       _valid_13_6_3 <= 0;
diff --git a/sample/tests/lib_fsm/delayed_lazy_cond/led.py b/sample/tests/lib_fsm/delayed_lazy_cond/led.py
@@ -37,7 +37,7 @@ def mkLed():
         fsm.add( valid(0), cond=c, delay=4, lazy_cond=True )
         fsm.goto_next(cond=c)
     
-    fsm.make_always(clk, rst, body=[count(count+1)])
+    fsm.make_always(clk, rst, reset=[count.reset()], body=[count(count+1)])
 
     return m
 
diff --git a/sample/tests/lib_fsm/delayed_lazy_cond/test_led.py b/sample/tests/lib_fsm/delayed_lazy_cond/test_led.py
@@ -80,13 +80,13 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      valid <= 0;
       count <= 0;
       fsm <= fsm_init;
       _d1_fsm <= fsm_init;
       _d2_fsm <= fsm_init;
       _d3_fsm <= fsm_init;
       _d4_fsm <= fsm_init;
+      valid <= 0;
     end else begin
       count <= count + 1;
       _d1_fsm <= fsm;
diff --git a/sample/tests/lib_fsm/prev/test_led.py b/sample/tests/lib_fsm/prev/test_led.py
@@ -63,10 +63,10 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      valid <= 0;
       fsm <= fsm_init;
-      _valid_1 <= 0;
       _d1_fsm <= fsm_init;
+      valid <= 0;
+      _valid_1 <= 0;
     end else begin
       _valid_1 <= valid;
       _d1_fsm <= fsm;
diff --git a/veriloggen/lib/fsm.py b/veriloggen/lib/fsm.py
@@ -6,6 +6,8 @@
 sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
 
 import vtypes
+import subst_visitor
+import reset_visitor
 import lib.parallel
 
 class FSM(vtypes.VeriloggenNode):
@@ -27,6 +29,10 @@ def __init__(self, m, name, width=32, initname='init'):
         self.delayed_body = collections.defaultdict(
             functools.partial(collections.defaultdict, list)) # key:delay
         self.tmp_count = 0
+        
+        self.dst_var = collections.OrderedDict()
+        self.dst_visitor = subst_visitor.SubstDstVisitor()
+        self.reset_visitor = reset_visitor.ResetVisitor()
 
         self.par = lib.parallel.Parallel(self.m, self.name + '_par')
 
@@ -85,6 +91,15 @@ def goto_next(self, cond=None):
     def prev(self, var, delay, initval=0):
         return self.par.prev(var, delay, initval)
         
+    #---------------------------------------------------------------------------
+    def add_dst_var(self, statement):
+        for s in statement:
+            values = self.dst_visitor.visit(s)
+            for v in values:
+                k = str(v)
+                if k not in self.dst_var:
+                    self.dst_var[k] = v
+                
     #---------------------------------------------------------------------------
     def add_delayed_cond(self, statement, index, delay):
         name_prefix = '_'.join(['', self.name, 'cond', str(index), str(self.tmp_count)])
@@ -150,13 +165,15 @@ def add(self, *statement, **kwargs):
                     cond = self.add_delayed_cond(cond, index, delay)
                 statement = [ vtypes.If(cond)(*statement) ]
             self.delayed_body[delay][index].extend(statement)
+            self.add_dst_var(statement)
             return self
             
         if cond is not None:
             statement = [ vtypes.If(cond)(*statement) ]
             
         index = self.current()
         self.body[index].extend(statement)
+        self.add_dst_var(statement)
         return self
 
     #---------------------------------------------------------------------------
@@ -193,12 +210,38 @@ def make_if(self):
                      for index in sorted(self.body.keys(), key=lambda x:x) ])
         return tuple(ret)
 
+    #---------------------------------------------------------------------------
+    def make_reset(self):
+        ret = collections.OrderedDict()
+        
+        v = self.reset_visitor.visit(self.state)
+        key = str(self.state)
+        if v is not None and key not in ret:
+            ret[key] = v
+            
+        for key, dst in self.delayed_state.items():
+            v = self.reset_visitor.visit(dst)
+            if v is not None and key not in ret:
+                ret[key] = v
+
+        for key, dst in self.dst_var.items():
+            v = self.reset_visitor.visit(dst)
+            if v is not None and key not in ret:
+                ret[key] = v
+
+        for v in self.par.make_reset():
+            key = str(v.left)
+            if v is not None and key not in ret:
+                ret[key] = v
+            
+        return list(ret.values())
+        
     #---------------------------------------------------------------------------
     def make_always(self, clk, rst, reset=(), body=(), case=True):
         self.m.Always(vtypes.Posedge(clk))(
             vtypes.If(rst)(
                 reset,
-                self.m.make_reset()
+                self.make_reset()
             )(
                 body,
                 self.make_case() if case else self.make_if()
@@ -253,6 +296,7 @@ def add_delayed_state(self, value):
             d = self.m.Reg(''.join(['_d', str(i), '_', self.name]), self.width,
                            initval=self.get_mark(0))
             self.delayed_state[i] = d
+            ###self.add_dst_var( [d] )
 
         self.delay_amount = value
         return d
