TmpReg, TmpWire, and etc are implemented: signal definition without a specific name

Author: shtaxxx

sample/tests/noname/Makefile

@@ -0,0 +1,30 @@
+TARGET=led.py
+TEST=test_led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out

sample/tests/noname/led.py

@@ -0,0 +1,42 @@
+import sys
+import os
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.TmpReg(32)
+
+    for i in range(3):
+        m.TmpReg(32)
+        m.TmpWire(32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            If(count == 1023)(
+                count(0)
+            ).Else(
+                count(count + 1)
+            )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(0)
+        ).Else(
+            If(count == 1024 - 1)(
+                led(led + 1)
+            )
+        ))
+    
+    return m
+
+if __name__ == '__main__':
+    led = mkLed()
+    verilog = led.to_verilog()
+    print(verilog)

sample/tests/noname/test_led.py

@@ -0,0 +1,54 @@
+import led
+
+expected_verilog = """
+module blinkled #
+  ( 
+   parameter WIDTH = 8
+  )
+  ( 
+   input CLK, 
+   input RST,
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] tmp_0;
+  reg [32-1:0] tmp_1;
+  wire [32-1:0] tmp_2;
+  reg [32-1:0] tmp_3;
+  wire [32-1:0] tmp_4;
+  reg [32-1:0] tmp_5;
+  wire [32-1:0] tmp_6;
+  always @(posedge CLK) begin
+    if(RST) begin
+      tmp_0 <= 0;
+    end else begin
+      if(tmp_0 == 1023) begin
+        tmp_0 <= 0;
+      end else begin
+        tmp_0 <= tmp_0 + 1;
+      end
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      if(tmp_0 == 1023) begin
+        LED <= LED + 1;
+      end 
+    end
+  end
+endmodule
+"""
+
+def test_led():
+    led_module = led.mkLed()
+    led_code = led_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == led_code)

sample/tests/noname/veriloggen

@@ -0,0 +1 @@
+../../../veriloggen

veriloggen/lib/__init__.py

@@ -14,5 +14,6 @@
 ## Please add import notations here for additional library
 from bundle import Bundle
 from fsm import FSM
+from pipeline import Pipeline
 import simulation
 

veriloggen/module.py

@@ -28,6 +28,7 @@ def __init__(self, name=None):
         self.submodule = collections.OrderedDict()
         self.generate = collections.OrderedDict()
         self.items = []
+        self.tmp_count = 0
 
     #---------------------------------------------------------------------------
     def Input(self, name, width=None, length=None, signed=False, value=None):
@@ -63,30 +64,55 @@ def Wire(self, name, width=None, length=None, signed=False, value=None):
         self.items.append(t)
         return t
 
+    def TmpWire(self, width=None, length=None, signed=False, value=None):
+        name = '_'.join(['tmp', str(self.tmp_count)])
+        self.tmp_count += 1
+        return self.Wire(name, width, length, signed, value)
+
     def Reg(self, name, width=None, length=None, signed=False, value=None, initval=None):
         t = vtypes.Reg(name, width, length, signed, value, initval)
         self.variable[name] = t
         self.items.append(t)
         return t
 
+    def TmpReg(self, width=None, length=None, signed=False, value=None, initval=None):
+        name = '_'.join(['tmp', str(self.tmp_count)])
+        self.tmp_count += 1
+        return self.Reg(name, width, length, signed, value, initval)
+
     def Integer(self, name, width=None, length=None, signed=False, value=None, initval=None):
         t = vtypes.Integer(name, width, length, signed, value, initval)
         self.variable[name] = t
         self.items.append(t)
         return t
 
+    def TmpInteger(self, width=None, length=None, signed=False, value=None, initval=None):
+        name = '_'.join(['tmp', str(self.tmp_count)])
+        self.tmp_count += 1
+        return self.Integer(name, width, length, signed, value, initval)
+
     def Real(self, name, width=None, length=None, signed=False, value=None, initval=None):
         t = vtypes.Real(name, width, length, signed, value, initval)
         self.variable[name] = t
         self.items.append(t)
         return t
 
+    def TmpReal(self, width=None, length=None, signed=False, value=None, initval=None):
+        name = '_'.join(['tmp', str(self.tmp_count)])
+        self.tmp_count += 1
+        return self.Real(name, width, length, signed, value, initval)
+
     def Genvar(self, name, width=None, length=None, signed=False, value=None):
         t = vtypes.Genvar(name, width, length, signed, value)
         self.variable[name] = t
         self.items.append(t)
         return t
 
+    def TmpGenvar(self, width=None, length=None, signed=False, value=None):
+        name = '_'.join(['tmp', str(self.tmp_count)])
+        self.tmp_count += 1
+        return self.Genvar(name, width, length, signed, value)
+
     def Parameter(self, name, value, width=None, signed=False, length=None):
         t = vtypes.Parameter(name, value, width, signed)
         self.global_constant[name] = t
@@ -99,6 +125,11 @@ def Localparam(self, name, value, width=None, signed=False, length=None):
         self.items.append(t)
         return t
 
+    def TmpLocalparam(self, value, width=None, signed=False, length=None):
+        name = '_'.join(['tmp', str(self.tmp_count)])
+        self.tmp_count += 1
+        return self.Localparam(name, value, width, signed, length)
+
     #---------------------------------------------------------------------------
     def Always(self, *sensitivity):
         t = vtypes.Always(*sensitivity)