First example "hello_led.py is updated."

Author: shtaxxx

Makefile

@@ -4,7 +4,7 @@ clean:
 	make clean -C ./utils
 	make clean -C ./examples
 	make clean -C ./tests
-	rm -rf *.pyc __pycache__ *.out uut.vcd veriloggen.egg-info build dist
+	rm -rf *.pyc __pycache__ *.out uut.vcd tmp.v veriloggen.egg-info build dist
 
 .PHONY: release
 release:

README.md

@@ -43,13 +43,13 @@ Install on your platform. For exmple, on Ubuntu:
 
 - Jinja2: 2.8 or later
 
-Install on your python environment by using pip.
+Install on your python environment by using pip:
 
     pip install jinja2
 
-- Pyverilog: 1.0.1 or later
+- Pyverilog: 1.0.2 or later
 
-Install from pip:
+Install from pip (or download from GitHub):
 
     pip install pyverilog
 
@@ -59,22 +59,22 @@ Options
 - pytest: 2.8.2 or later
 - pytest-pythonpath: 0.7 or later
 
-These softwares are required for running the tests in tests and examples.
+These softwares are required for running the tests in tests and examples:
 
     pip install pytest pytest-pythonpath
 
 - Graphviz: 2.38.0 or later
 - Pygraphviz: 1.3.1 or later
 
-These softwares are required for graph visualization by lib.dataflow.
+These softwares are required for graph visualization by lib.dataflow:
 
     sudo apt-get install graphviz
     pip install pygraphviz
 
 Install
 --------------------
 
-Install Veriloggen.
+Install Veriloggen:
 
     python setup.py install
 
@@ -101,6 +101,8 @@ Let's begin veriloggen by an example. Create a example Python script in Python a
 Open 'hello_led.py' in the root directory.
 
 ```python
+from __future__ import absolute_import
+from __future__ import print_function
 import sys
 import os
 from veriloggen import *
@@ -133,44 +135,137 @@ def mkLed():
             )
         ))
 
+    m.Always(Posedge(clk))(
+        If(rst)(
+        ).Else(
+            Systask('display', "LED:%d count:%d", led, count)
+        ))
+    
     return m
 
-if __name__ == '__main__':
+def mkTest():
+    m = Module('test')
+    
+    # target instance
     led = mkLed()
-    # led.to_verilog(filename='tmp.v')
-    verilog = led.to_verilog()
+    
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+    
+    clk = ports['CLK']
+    rst = ports['RST']
+    
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+    
+    lib.simulation.setup_waveform(m, uut, m.get_vars())
+    lib.simulation.setup_clock(m, clk, hperiod=5)
+    init = lib.simulation.setup_reset(m, rst, m.make_reset(), period=100)
+    
+    init.add(
+        Delay(1000 * 100),
+        Systask('finish'),
+    )
+
+    return m
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog(filename='tmp.v')
+    #verilog = test.to_verilog()
     print(verilog)
+
+    sim = lib.simulation.Simulator(test)
+    rslt = sim.run()
+    print(rslt)
+
+    #sim.view_waveform()
 ```
 
 Run the script.
 
 ```
-python led.py
+python hello_led.py
 ```
 
-You will have a complete Verilog HDL source code that is generated by the source code generator.
+You will have a complete Verilog HDL source code named 'tmp.v' in the root directory, which is generated by the source code generator.
 
 ```verilog
+module test #
+(
+  parameter WIDTH = 8
+)
+(
+
+);
+
+  reg CLK;
+  reg RST;
+  wire [WIDTH - 1:0] LED;
+
+  blinkled
+  #(
+    .WIDTH(WIDTH)
+  )
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .LED(LED)
+  );
+
+
+  initial begin
+    $dumpfile("uut.vcd");
+    $dumpvars(0, uut, CLK, RST, LED);
+  end
+
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = !CLK;
+    end
+  end
+
+
+  initial begin
+    RST = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #100000;
+    $finish;
+  end
+
+
+endmodule
+
+
+
 module blinkled #
 (
   parameter WIDTH = 8
 )
 (
   input CLK,
   input RST,
-  output reg [(WIDTH - 1):0] LED
+  output reg [WIDTH - 1:0] LED
 );
 
-  reg [(32 - 1):0] count;
+  reg [32 - 1:0] count;
 
   always @(posedge CLK) begin
     if(RST) begin
       count <= 0;
     end else begin
-      if((count == 1023)) begin
+      if(count == 1023) begin
         count <= 0;
       end else begin
-        count <= (count + 1);
+        count <= count + 1;
       end
     end
   end
@@ -180,13 +275,21 @@ module blinkled #
     if(RST) begin
       LED <= 0;
     end else begin
-      if((count == 1023)) begin
-        LED <= (LED + 1);
+      if(count == 1023) begin
+        LED <= LED + 1;
       end 
     end
   end
 
 
+  always @(posedge CLK) begin
+    if(RST) begin
+    end else begin
+      $display("LED:%d count:%d", LED, count);
+    end
+  end
+
+
 endmodule
 ```