Properly reset qubits in squin runtime

Author: david-pl

src/bloqade/pyqrack/squin/qubit.py

@@ -71,15 +71,23 @@ def measure_and_reset(
         result = []
         for qbit in qubits:
             if qbit.is_active():
-                result.append(qbit.sim_reg.m(qbit.addr))
+                qbit_result = bool(qbit.sim_reg.m(qbit.addr))
             else:
-                result.append(None)
-            qbit.sim_reg.force_m(qbit.addr, 0)
+                qbit_result = None
+
+            if qbit_result:
+                qbit.sim_reg.x(qbit.addr)
+
+            result.append(qbit_result)
 
         return (ilist.IList(result),)
 
     @interp.impl(qubit.Reset)
     def reset(self, interp: PyQrackInterpreter, frame: interp.Frame, stmt: qubit.Reset):
         qubits: ilist.IList[PyQrackQubit, Any] = frame.get(stmt.qubits)
         for qbit in qubits:
-            qbit.sim_reg.force_m(qbit.addr, 0)
+            if not qbit.is_active():
+                continue
+
+            if bool(qbit.sim_reg.m(qbit.addr)):
+                qbit.sim_reg.x(qbit.addr)

src/bloqade/pyqrack/squin/wire.py

@@ -43,7 +43,7 @@ def measure(
     ):
         w: PyQrackWire = frame.get(stmt.wire)
         qbit = w.qubit
-        res: int = qbit.sim_reg.m(qbit.addr)
+        res: bool = bool(qbit.sim_reg.m(qbit.addr))
         return (res,)
 
     @interp.impl(wire.MeasureAndReset)
@@ -55,15 +55,22 @@ def measure_and_reset(
     ):
         w: PyQrackWire = frame.get(stmt.wire)
         qbit = w.qubit
-        res: int = qbit.sim_reg.m(qbit.addr)
-        qbit.sim_reg.force_m(qbit.addr, False)
+        res: bool = bool(qbit.sim_reg.m(qbit.addr))
+
+        if res:
+            qbit.sim_reg.x(qbit.addr)
+
+        # TODO: do we need to rewrap this here? The qbit changed in-place
         new_w = PyQrackWire(qbit)
         return (new_w, res)
 
     @interp.impl(wire.Reset)
     def reset(self, interp: PyQrackInterpreter, frame: interp.Frame, stmt: wire.Reset):
         w: PyQrackWire = frame.get(stmt.wire)
         qbit = w.qubit
-        qbit.sim_reg.force_m(qbit.addr, False)
+
+        if bool(qbit.sim_reg.m(qbit.addr)):
+            qbit.sim_reg.x(qbit.addr)
+
         new_w = PyQrackWire(qbit)
         return (new_w,)