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Release/0.13.1
2 parents f5c9751 + ce6106f commit c7d4380

20 files changed

+195
-76
lines changed

perceval/components/abstract_processor.py

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -340,7 +340,8 @@ def check_input(self, input_state: BasicState):
340340

341341
def check_min_detected_photons_filter(self):
342342
if self._min_detected_photons_filter is None:
343-
if not self.is_remote and self._source is not None and self._source.is_perfect():
343+
if (not self.is_remote and self._source is not None and self._source.is_perfect()
344+
and isinstance(self.input_state, BasicState)):
344345
# Automatically set the min_detected_photons_filter for perfect sources of local processors if not set
345346
self.min_detected_photons_filter(self.input_state.n)
346347
else:

perceval/components/component_catalog.py

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@
3030
from abc import ABC, abstractmethod
3131

3232
from perceval.utils import Parameter
33-
from perceval.components import Processor, Circuit
33+
from perceval.components import Processor, Circuit, Experiment
3434
from perceval.utils.logging import get_logger, channel
3535

3636

@@ -80,10 +80,6 @@ def _handle_param(value):
8080
return Parameter(value)
8181
return value
8282

83-
def _init_processor(self, **kwargs):
84-
return Processor(kwargs.get("backend", self._default_backend), self.build_circuit(**kwargs),
85-
name=kwargs.get("name") or self._name.upper())
86-
8783
@abstractmethod
8884
def build_circuit(self, **kwargs) -> Circuit:
8985
"""Build the component as circuit
@@ -93,6 +89,13 @@ def build_circuit(self, **kwargs) -> Circuit:
9389
pass
9490

9591
@abstractmethod
92+
def build_experiment(self, **kwargs) -> Experiment:
93+
"""Build the component as experiment
94+
95+
:return: A Perceval experiment
96+
"""
97+
pass
98+
9699
def build_processor(self, **kwargs) -> Processor:
97100
"""Build the component as processor
98101
@@ -101,7 +104,8 @@ def build_processor(self, **kwargs) -> Processor:
101104
102105
:return: A Perceval processor
103106
"""
104-
pass
107+
return Processor(kwargs.get("backend", self._default_backend), self.build_experiment(**kwargs),
108+
name=kwargs.get("name") or self._name.upper())
105109

106110

107111
class Catalog:

perceval/components/core_catalog/controlled_rotation_gates.py

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@
3434
import cmath as cm
3535
from scipy.linalg import block_diag
3636

37-
from perceval.components import Circuit, Port, Unitary
37+
from perceval.components import Circuit, Port, Unitary, Processor, Experiment
3838
from perceval.components.component_catalog import CatalogItem
3939
from perceval.utils import Encoding, PostSelect, Matrix
4040

@@ -93,7 +93,7 @@ class PostProcessedControlledRotationsItem(CatalogItem):
9393
def __init__(self):
9494
super().__init__("postprocessed controlled gate")
9595

96-
def build_circuit(self, **kwargs):
96+
def build_circuit(self, **kwargs) -> Circuit:
9797
"""
9898
kwargs:
9999
- n : int, number of qubit of the gate.
@@ -116,17 +116,17 @@ def build_circuit(self, **kwargs):
116116
m = build_control_gate_unitary(n, alpha)
117117
return Circuit(4*n, name="postprocessed controlled gate").add(0, Unitary(m))
118118

119-
def build_processor(self, **kwargs):
120-
p = self._init_processor(**kwargs)
119+
def build_experiment(self, **kwargs) -> Experiment:
120+
e = Experiment(self.build_circuit(**kwargs))
121121
n = kwargs["n"]
122122

123-
p.set_postselection(PostSelect('&'.join([f"[{2*n},{2*n+1}]==1" for n in range(n)])))
123+
e.set_postselection(PostSelect('&'.join([f"[{2*n},{2*n+1}]==1" for n in range(n)])))
124124

125125
for i in range(n - 1):
126-
p.add_port(2 * i, Port(Encoding.DUAL_RAIL, f"ctrl{i}"))
127-
p.add_port(2 * (n - 1), Port(Encoding.DUAL_RAIL, "data"))
126+
e.add_port(2 * i, Port(Encoding.DUAL_RAIL, f"ctrl{i}"))
127+
e.add_port(2 * (n - 1), Port(Encoding.DUAL_RAIL, "data"))
128128

129129
for i in range(2 * n, 4 * n):
130-
p.add_herald(i, 0)
130+
e.add_herald(i, 0)
131131

132-
return p
132+
return e

perceval/components/core_catalog/gates_1qubit.py

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@
3131
from abc import ABC, abstractmethod
3232
from numbers import Number
3333

34-
from perceval.components import Processor, Circuit, BS, PS, PERM, Port
34+
from perceval.components import Processor, Circuit, BS, PS, PERM, Port, Experiment
3535
from perceval.utils import Encoding, P
3636
from perceval.components.component_catalog import CatalogItem
3737

@@ -73,9 +73,10 @@ def description(self):
7373
def str_repr(self):
7474
return _get_component_str_repr(self.repr_name)
7575

76-
def build_processor(self, **kwargs) -> Processor:
77-
p = self._init_processor(**kwargs)
78-
return p.add_port(0, Port(Encoding.DUAL_RAIL, 'data'))
76+
def build_experiment(self, **kwargs) -> Experiment:
77+
e = Experiment(self.build_circuit(**kwargs))
78+
return e.add_port(0, Port(Encoding.DUAL_RAIL, 'data'))
79+
7980

8081

8182
class AFixedItem(ASingleQubitGate, ABC):
@@ -158,7 +159,7 @@ class AParamItem(ASingleQubitGate, ABC):
158159
def get_circuit(self, param) -> Circuit:
159160
pass
160161

161-
def build_circuit(self, **kwargs):
162+
def build_circuit(self, **kwargs) -> Circuit:
162163
param = kwargs.get(self.param_key, 0.0)
163164
param = self._handle_param(param)
164165
name = self.repr_name

perceval/components/core_catalog/generic_2mode.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
2828
# SOFTWARE.
2929

30-
from perceval.components import Circuit, BS
30+
from perceval.components import Circuit, BS, Processor, Experiment
3131
from perceval.components.component_catalog import CatalogItem
3232

3333

@@ -49,12 +49,12 @@ class Generic2ModeItem(CatalogItem):
4949
def __init__(self):
5050
super().__init__("generic 2 mode circuit")
5151

52-
def build_circuit(self, **kwargs):
52+
def build_circuit(self, **kwargs) -> Circuit:
5353
return Circuit(2, name=kwargs.get("name", "U2")) \
5454
// BS.H(theta=self._handle_param(kwargs.get("theta", "theta")),
5555
phi_tl=self._handle_param(kwargs.get("phi_tl", "phi_tl")),
5656
phi_bl=self._handle_param(kwargs.get("phi_bl", "phi_bl")),
5757
phi_tr=self._handle_param(kwargs.get("phi_tr", "phi_tr")))
5858

59-
def build_processor(self, **kwargs):
60-
return self._init_processor(**kwargs)
59+
def build_experiment(self, **kwargs) -> Experiment:
60+
return Experiment(self.build_circuit(**kwargs))

perceval/components/core_catalog/heralded_cnot.py

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,8 @@
3030
from perceval.components import Circuit, BS, Port
3131
from perceval.components.component_catalog import CatalogItem
3232
from perceval.components.core_catalog.heralded_cz import HeraldedCzItem
33+
from perceval.components.experiment import Experiment
34+
from perceval.components.processor import Processor
3335
from perceval.utils import Encoding
3436

3537

@@ -48,17 +50,17 @@ class HeraldedCnotItem(CatalogItem):
4850
def __init__(self):
4951
super().__init__("heralded cnot")
5052

51-
def build_circuit(self, **kwargs):
53+
def build_circuit(self, **kwargs) -> Circuit:
5254
c = Circuit(6, name="Heralded CNOT")
5355
c.add(2, BS.H())
5456
heralded_cz = HeraldedCzItem()
5557
c.add(0, heralded_cz.build_circuit(), merge=True)
5658
c.add(2, BS.H())
5759
return c
5860

59-
def build_processor(self, **kwargs):
60-
p = self._init_processor(**kwargs)
61-
return p.add_port(0, Port(Encoding.DUAL_RAIL, 'ctrl'))\
61+
def build_experiment(self, **kwargs) -> Experiment:
62+
e = Experiment(self.build_circuit(**kwargs))
63+
return e.add_port(0, Port(Encoding.DUAL_RAIL, 'ctrl'))\
6264
.add_port(2, Port(Encoding.DUAL_RAIL, 'data'))\
6365
.add_herald(4, 1)\
6466
.add_herald(5, 1)

perceval/components/core_catalog/heralded_cz.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929

3030
import math
3131

32-
from perceval.components import Processor, Circuit, PERM, BS, PS, Barrier
32+
from perceval.components import Processor, Circuit, PERM, BS, PS, Barrier, Experiment
3333
from perceval.components.component_catalog import CatalogItem
3434
from perceval.components.port import Port, Encoding
3535

@@ -71,9 +71,9 @@ def build_circuit(self, **kwargs) -> Circuit:
7171
.add(2, last_modes_cz, merge=True)
7272
.add(1, PERM([1, 0])))
7373

74-
def build_processor(self, **kwargs) -> Processor:
75-
p = self._init_processor(**kwargs)
76-
return p.add_port(0, Port(Encoding.DUAL_RAIL, 'ctrl')) \
74+
def build_experiment(self, **kwargs) -> Experiment:
75+
e = Experiment(self.build_circuit(**kwargs))
76+
return e.add_port(0, Port(Encoding.DUAL_RAIL, 'ctrl')) \
7777
.add_port(2, Port(Encoding.DUAL_RAIL, 'data')) \
7878
.add_herald(4, 1) \
7979
.add_herald(5, 1)

perceval/components/core_catalog/klm_cnot.py

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929

3030
from math import sqrt
3131

32-
from perceval.components import Circuit, BS, PERM, Port
32+
from perceval.components import Circuit, BS, PERM, Port, Processor, Experiment
3333
from perceval.components.component_catalog import CatalogItem
3434
from perceval.utils import Encoding
3535

@@ -58,7 +58,7 @@ class KLMCnotItem(CatalogItem):
5858
def __init__(self):
5959
super().__init__("klm cnot")
6060

61-
def build_circuit(self, **kwargs):
61+
def build_circuit(self, **kwargs) -> Circuit:
6262
return (Circuit(8, name=_GATE_NAME)
6363
.add(1, PERM([2, 4, 3, 0, 1]))
6464
.add(4, BS.H())
@@ -77,9 +77,9 @@ def build_circuit(self, **kwargs):
7777
.add(4, BS.H())
7878
.add(1, PERM([4, 3, 0, 2, 1])))
7979

80-
def build_processor(self, **kwargs):
81-
p = self._init_processor(**kwargs)
82-
return p.add_port(0, Port(Encoding.DUAL_RAIL, 'ctrl')) \
80+
def build_experiment(self, **kwargs) -> Experiment:
81+
e = Experiment(self.build_circuit(**kwargs))
82+
return e.add_port(0, Port(Encoding.DUAL_RAIL, 'ctrl')) \
8383
.add_port(2, Port(Encoding.DUAL_RAIL, 'data')) \
8484
.add_herald(4, 0) \
8585
.add_herald(5, 1) \

perceval/components/core_catalog/mzi.py

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@
3131
from abc import ABC
3232

3333

34-
from perceval.components import Processor, Circuit, BS, PS
34+
from perceval.components import Processor, Circuit, BS, PS, Experiment
3535
from perceval.components.component_catalog import CatalogItem
3636

3737

@@ -54,8 +54,8 @@ def _handle_params(**kwargs):
5454
CatalogItem._handle_param(kwargs.get("theta_a", math.pi/2)), \
5555
CatalogItem._handle_param(kwargs.get("theta_b", math.pi/2))
5656

57-
def build_processor(self, **kwargs) -> Processor:
58-
return self._init_processor(**kwargs)
57+
def build_experiment(self, **kwargs) -> Experiment:
58+
return Experiment(self.build_circuit(**kwargs))
5959

6060
def generate(self, i: int):
6161
return self.build_circuit(i=i)

perceval/components/core_catalog/postprocessed_ccz.py

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929

3030
from math import pi
3131

32-
from perceval.components import Circuit, Port, Unitary
32+
from perceval.components import Circuit, Port, Unitary, Processor, Experiment
3333
from perceval.components.component_catalog import CatalogItem
3434
from perceval.components.core_catalog import controlled_rotation_gates
3535
from perceval.utils import Encoding, PostSelect, Matrix
@@ -52,14 +52,14 @@ class PostProcessedCCZItem(CatalogItem):
5252
def __init__(self):
5353
super().__init__("postprocessed ccz")
5454

55-
def build_circuit(self, **kwargs):
55+
def build_circuit(self, **kwargs) -> Circuit:
5656
m = Matrix(controlled_rotation_gates.build_control_gate_unitary(3, pi))
5757
return Circuit(12, name="PostProcessed CCZ").add(0, Unitary(m))
5858

59-
def build_processor(self, **kwargs):
60-
p = self._init_processor(**kwargs)
61-
p.set_postselection(PostSelect("[0,1]==1 & [2,3]==1 & [4,5]==1"))
62-
return p.add_port(0, Port(Encoding.DUAL_RAIL, 'ctrl0')) \
59+
def build_experiment(self, **kwargs) -> Experiment:
60+
e = Experiment(self.build_circuit(**kwargs))
61+
e.set_postselection(PostSelect("[0,1]==1 & [2,3]==1 & [4,5]==1"))
62+
return e.add_port(0, Port(Encoding.DUAL_RAIL, 'ctrl0')) \
6363
.add_port(2, Port(Encoding.DUAL_RAIL, 'ctrl1')) \
6464
.add_port(4, Port(Encoding.DUAL_RAIL, 'data')) \
6565
.add_herald(6, 0) \

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