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RASPIAUDIOadminRASPIAUDIOadmin
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2 files changed

+52
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‎src/museS3.cpp‎

Lines changed: 31 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -130,46 +130,46 @@ bool ES8388::begin(int sda, int scl, uint32_t frequency)
130130
{
131131

132132
/* mute DAC during setup, power up all systems, slave mode */
133-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL3, 0x04);
134-
res &= write_reg(ES8388_ADDR, ES8388_CONTROL2, 0x50);
135-
res &= write_reg(ES8388_ADDR, ES8388_CHIPPOWER, 0x00);
136-
res &= write_reg(ES8388_ADDR, ES8388_MASTERMODE, 0x00);
133+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL3, 0x04);
134+
res |= write_reg(ES8388_ADDR, ES8388_CONTROL2, 0x50);
135+
res |= write_reg(ES8388_ADDR, ES8388_CHIPPOWER, 0x00);
136+
res |= write_reg(ES8388_ADDR, ES8388_MASTERMODE, 0x00);
137137

138138
/* power up DAC and enable LOUT1+2 / ROUT1+2, ADC sample rate = DAC sample rate */
139-
res &= write_reg(ES8388_ADDR, ES8388_DACPOWER, 0x3e);
140-
res &= write_reg(ES8388_ADDR, ES8388_CONTROL1, 0x12);
139+
res |= write_reg(ES8388_ADDR, ES8388_DACPOWER, 0x3e);
140+
res |= write_reg(ES8388_ADDR, ES8388_CONTROL1, 0x12);
141141

142142
/* DAC I2S setup: 16 bit word length, I2S format; MCLK / Fs = 256*/
143-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL1, 0x18);
144-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL2, 0x02);
143+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL1, 0x18);
144+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL2, 0x02);
145145

146146
/* DAC to output route mixer configuration: ADC MIX TO OUTPUT */
147-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL16, 0x1B);
148-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL17, 0x90);
149-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL20, 0x90);
147+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL16, 0x1B);
148+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL17, 0x90);
149+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL20, 0x90);
150150

151151
/* DAC and ADC use same LRCK, enable MCLK input; output resistance setup */
152-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL21, 0x80);
153-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL23, 0x00);
152+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL21, 0x80);
153+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL23, 0x00);
154154

155155
/* DAC volume control: 0dB (maximum, unattenuated) */
156-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL5, 0x00);
157-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL4, 0x00);
156+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL5, 0x00);
157+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL4, 0x00);
158158

159159
/* power down ADC while configuring; volume: +9dB for both channels */
160-
res &= write_reg(ES8388_ADDR, ES8388_ADCPOWER, 0xff);
161-
res &= write_reg(ES8388_ADDR, ES8388_ADCCONTROL1, 0x88); // +24db
160+
res |= write_reg(ES8388_ADDR, ES8388_ADCPOWER, 0xff);
161+
res |= write_reg(ES8388_ADDR, ES8388_ADCCONTROL1, 0x88); // +24db
162162

163163
// differential, stereo, Right => LINPUT1/RINPUT1 , Left => LINPUT2/RINPUT2
164-
res &= write_reg(ES8388_ADDR, ES8388_ADCCONTROL2, 0xFC); //
165-
res &= write_reg(ES8388_ADDR, ES8388_ADCCONTROL3, 0x02); // 00
164+
res |= write_reg(ES8388_ADDR, ES8388_ADCCONTROL2, 0xFC); //
165+
res |= write_reg(ES8388_ADDR, ES8388_ADCCONTROL3, 0x02); // 00
166166

167-
res &= write_reg(ES8388_ADDR, ES8388_ADCCONTROL4, 0x0c);
168-
res &= write_reg(ES8388_ADDR, ES8388_ADCCONTROL5, 0x02);
167+
res |= write_reg(ES8388_ADDR, ES8388_ADCCONTROL4, 0x0c);
168+
res |= write_reg(ES8388_ADDR, ES8388_ADCCONTROL5, 0x02);
169169

170170
/* set ADC volume */
171-
res &= write_reg(ES8388_ADDR, ES8388_ADCCONTROL8, 0x00);
172-
res &= write_reg(ES8388_ADDR, ES8388_ADCCONTROL9, 0x00);
171+
res |= write_reg(ES8388_ADDR, ES8388_ADCCONTROL8, 0x00);
172+
res |= write_reg(ES8388_ADDR, ES8388_ADCCONTROL9, 0x00);
173173

174174
// ALC
175175
// (optimized for voice)
@@ -182,20 +182,20 @@ bool ES8388::begin(int sda, int scl, uint32_t frequency)
182182

183183

184184
// Set mono => (R + L) / 2
185-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL7, 0x20);
185+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL7, 0x20);
186186

187187
/* set LOUT1 / ROUT1 volume: 0dB (unattenuated) */
188-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL24, 0x21);
189-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL25, 0x21);
188+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL24, 0x21);
189+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL25, 0x21);
190190

191191
/* set LOUT2 / ROUT2 volume: 0dB (unattenuated) */
192-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL26, 0x21);
193-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL27, 0x21);
192+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL26, 0x21);
193+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL27, 0x21);
194194

195195
/* power up and enable DAC; power up ADC (no MIC bias) */
196-
res &= write_reg(ES8388_ADDR, ES8388_DACPOWER, 0x3C);
197-
res &= write_reg(ES8388_ADDR, ES8388_DACCONTROL3, 0x00);
198-
res &= write_reg(ES8388_ADDR, ES8388_ADCPOWER, 0x00);
196+
res |= write_reg(ES8388_ADDR, ES8388_DACPOWER, 0x3C);
197+
res |= write_reg(ES8388_ADDR, ES8388_DACCONTROL3, 0x00);
198+
res |= write_reg(ES8388_ADDR, ES8388_ADCPOWER, 0x00);
199199

200200
/* set up MCLK) */
201201
// PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0_CLK_OUT1);

‎src/museWrover.cpp‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -177,44 +177,44 @@ bool ES8388::begin(int sda, int scl, uint32_t frequency)
177177
// DAC power-up LOUT1/ROUT1 enabled
178178
write_reg(ES8388_ADDR, 4, 0x30);
179179

180-
res &=write_reg(ES8388_ADDR, 8, 0x00); // ES8388 in I2S slave mode
181-
res &=write_reg(ES8388_ADDR, 43, 0x80); // Set ADC and DAC to have the same LRCK
182-
res &=write_reg(ES8388_ADDR, 0, 0x05); // Start up reference
183-
res &=write_reg(ES8388_ADDR, 1, 0x40); // Start up reference
184-
res &=write_reg(ES8388_ADDR, 3, 0x00); // Power on ADC and LIN/RIN input
185-
res &=write_reg(ES8388_ADDR, 9, 0x77); // MicBoost PGA = +21dB
186-
res &=write_reg(ES8388_ADDR, 10, 0x00); // LIN1 and RIN1 used as single-ended input
180+
res |=write_reg(ES8388_ADDR, 8, 0x00); // ES8388 in I2S slave mode
181+
res |=write_reg(ES8388_ADDR, 43, 0x80); // Set ADC and DAC to have the same LRCK
182+
res |=write_reg(ES8388_ADDR, 0, 0x05); // Start up reference
183+
res |=write_reg(ES8388_ADDR, 1, 0x40); // Start up reference
184+
res |=write_reg(ES8388_ADDR, 3, 0x00); // Power on ADC and LIN/RIN input
185+
res |=write_reg(ES8388_ADDR, 9, 0x77); // MicBoost PGA = +21dB
186+
res |=write_reg(ES8388_ADDR, 10, 0x00); // LIN1 and RIN1 used as single-ended input
187187

188188
//write_reg(ES8388_ADDR, 0x0A, 0x50); // LIN2 and RIN2 used as single-ended input
189-
res &=write_reg(ES8388_ADDR, 12, 0x00); // I2S – 24bits, Ldata = LADC, Rdata = RADC
190-
res &=write_reg(ES8388_ADDR, 13, 0x02); // MCLK/LRCK = 256
191-
res &=write_reg(ES8388_ADDR, 16, 0x00); // LADC volume = 0dB
192-
res &=write_reg(ES8388_ADDR, 17, 0x00); // RADC volume = 0dB
189+
res |=write_reg(ES8388_ADDR, 12, 0x00); // I2S – 24bits, Ldata = LADC, Rdata = RADC
190+
res |=write_reg(ES8388_ADDR, 13, 0x02); // MCLK/LRCK = 256
191+
res |=write_reg(ES8388_ADDR, 16, 0x00); // LADC volume = 0dB
192+
res |=write_reg(ES8388_ADDR, 17, 0x00); // RADC volume = 0dB
193193
// ALC
194194

195195
/*
196-
res &=write_reg(ES8388_ADDR, 18, 0xE2); // ALC enable, PGA Max. Gain=23.5dB, Min. Gain=0dB
197-
res &=write_reg(ES8388_ADDR, 19, 0xA0); // ALC Target=-4.5dB, ALC Hold time=0ms
198-
res &=write_reg(ES8388_ADDR, 20, 0x12); // Decay time=820µs, Attack time=416µs
199-
res &=write_reg(ES8388_ADDR, 21, 0x06); // ALC mode
200-
res &=write_reg(ES8388_ADDR, 22, 0xC3); // Noise gate=-40.5dB, NGG=0x01(mute ADC)
196+
res |=write_reg(ES8388_ADDR, 18, 0xE2); // ALC enable, PGA Max. Gain=23.5dB, Min. Gain=0dB
197+
res |=write_reg(ES8388_ADDR, 19, 0xA0); // ALC Target=-4.5dB, ALC Hold time=0ms
198+
res |=write_reg(ES8388_ADDR, 20, 0x12); // Decay time=820µs, Attack time=416µs
199+
res |=write_reg(ES8388_ADDR, 21, 0x06); // ALC mode
200+
res |=write_reg(ES8388_ADDR, 22, 0xC3); // Noise gate=-40.5dB, NGG=0x01(mute ADC)
201201
202202
*/
203203

204204
// 1) ALC enable, PGA max gain
205-
res &= write_reg(ES8388_ADDR, 18, 0xE2);
205+
res |= write_reg(ES8388_ADDR, 18, 0xE2);
206206

207207
// 2) ALC Target = 0 dB
208-
res &= write_reg(ES8388_ADDR, 19, 0xE0);
208+
res |= write_reg(ES8388_ADDR, 19, 0xE0);
209209

210210
// 3) Decay = 5,2 ms, Attack = 2,6 ms
211-
res &= write_reg(ES8388_ADDR, 20, 0x1E);
211+
res |= write_reg(ES8388_ADDR, 20, 0x1E);
212212

213213
// 4) ALC mode (restez en mode standard si besoin)
214-
res &= write_reg(ES8388_ADDR, 21, 0x06);
214+
res |= write_reg(ES8388_ADDR, 21, 0x06);
215215

216216
// 5) Noise gate : seuil –60 dB, hold gain, activé
217-
res &= write_reg(ES8388_ADDR, 22, 0x5B);
217+
res |= write_reg(ES8388_ADDR, 22, 0x5B);
218218

219219

220220

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