Apply suggestions from code review

Co-authored-by: crasbe <[email protected]>

Author: AnnsAnns

cpu/riscv_common/include/xh3irq.h

@@ -39,7 +39,7 @@ extern const void *vector_cpu[CPU_IRQ_NUMOF];
  * preemption level in meicontext.preempt.
  */
 #define MEIP_OFFSET 11
-/* Mask to extract the MEIP bit from MIP/MISE */
+/** Mask to extract the MEIP bit from MIP/MISE */
 #define MEIP_MASK 0x1
 /**
  * Index of the highest-priority active external interrupt.

cpu/riscv_common/irq_arch.c

@@ -97,7 +97,7 @@ __attribute((used)) static void handle_trap(uword_t mcause)
 
 #ifdef DEVELHELP
     printf("Trap: mcause=0x%" PRIx32 " mepc=0x%lx mtval=0x%lx\n",
-          (uint32_t)mcause, read_csr(mepc), read_csr(mtval));
+           (uint32_t)mcause, read_csr(mepc), read_csr(mtval));
 
     /* See https://riscv.github.io/riscv-isa-manual/snapshot/privileged/#mcause */
     if ((mcause & ~MCAUSE_INT) <= 0xb) {
@@ -132,8 +132,8 @@ __attribute((used)) static void handle_trap(uword_t mcause)
                 );
             } else {
                 printf("Machine Cause indicates that 0x%lx"
-                        " is a reserved or custom cause code\n",
-                        cause_code
+                       " is a reserved or custom cause code\n",
+                       cause_code
                 );
             }
         }

cpu/riscv_common/periph/xh3irq.c

@@ -15,8 +15,8 @@ uint32_t xh3irq_has_pending(void)
      * Get MEIP which is the external interrupt pending bit
      * from the Machine Interrupt Pending Register address
      */
-     uint32_t mip_reg = read_csr(0x344);
-     uint32_t meip = bit_check32(&mip_reg, MEIP_OFFSET);
+    uint32_t mip_reg = read_csr(0x344);
+    uint32_t meip = bit_check32(&mip_reg, MEIP_OFFSET);
 
     return (meip != 0);
 }

cpu/rp2350_riscv/include/cpu_conf.h

@@ -23,7 +23,7 @@ extern "C" {
 
 #define CPU_DEFAULT_IRQ_PRIO 1u
 #define CPU_IRQ_NUMOF 52u
-/* This tells rp2350_common that we are using the RISC-V core */
+/** This tells rp2350_common that we are using the RISC-V core */
 #define RP2350_USE_RISCV 1
 
 #ifdef __cplusplus