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chore(ads1x1x): static-tests fix
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5 files changed

+79
-111
lines changed

5 files changed

+79
-111
lines changed

‎drivers/ads1x1x/ads1x1x.c‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@
2424
#include "ztimer.h"
2525
#include "byteorder.h"
2626

27-
#define ENABLE_DEBUG 1
27+
#define ENABLE_DEBUG 0
2828
#include "debug.h"
2929

3030
#ifndef ADS1X1X_READ_DELAY_MS
@@ -261,7 +261,6 @@ int ads1x1x_read_raw(const ads1x1x_t *dev, int16_t *raw)
261261
/* Single-Shot mode */
262262
if ((reg & (ADS1X1X_MODE_MASK << 8)) == (ADS1X1X_MODE_SINGLE << 8)) {
263263

264-
265264
/* Tell the ADC to acquire a single-shot sample */
266265
reg |= (ADS1X1X_CONF_OS_CONV_MASK << 8);
267266
if (_write_config_reg(DEV, ADDR, reg) < 0) {

‎drivers/ads1x1x/ads1x1x_saul.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,6 @@ static int read_adc(const void *dev, phydat_t *res)
4141
return 1;
4242
}
4343

44-
4544
const saul_driver_t ads1x1x_saul_driver = {
4645
.read = read_adc,
4746
.write = saul_write_notsup,

‎drivers/ads1x1x/include/ads1x1x_internal.h‎

Lines changed: 53 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -26,165 +26,135 @@ extern "C" {
2626
* @name ADS101x/111x register addresses
2727
* @{
2828
*/
29-
#define ADS1X1X_CONV_RES_ADDR (0) /**< Conversion register */
30-
#define ADS1X1X_CONF_ADDR (1) /**< Configuration register */
31-
#define ADS1X1X_LOW_LIMIT_ADDR (2) /**< Low limit register */
32-
#define ADS1X1X_HIGH_LIMIT_ADDR (3) /**< High limit register */
29+
#define ADS1X1X_CONV_RES_ADDR (0) /**< Conversion register */
30+
#define ADS1X1X_CONF_ADDR (1) /**< Configuration register */
31+
#define ADS1X1X_LOW_LIMIT_ADDR (2) /**< Low limit register */
32+
#define ADS1X1X_HIGH_LIMIT_ADDR (3) /**< High limit register */
3333
/** @} */
3434

3535
/**
36-
* @name ADS101x/111x Operational Status
37-
*
38-
* This bit indicates the status of the conversion.
39-
*
40-
* @{
36+
* @brief ADS101x/111x Operational Status
4137
*/
42-
#define ADS1X1X_CONF_OS_CONV_MASK (1 << 7)
43-
44-
/** @} */
38+
#define ADS1X1X_CONF_OS_CONV_MASK (1 << 7) /**< Operational status bit */
4539

4640
/**
4741
* @name ADS101x/111x mux settings
48-
*
4942
* Supports both single mode and differential.
5043
* This has no effect on ADS1013-4 and ADS1113-4.
51-
*
5244
* @{
5345
*/
54-
#define ADS1X1X_MUX_MASK ((1 << 6) | (1 << 5) | (1 << 4))
55-
#define ADS1X1X_AIN0_DIFFM_AIN1 ((0 << 6) | (0 << 5) | (0 << 4))
56-
#define ADS1X1X_AIN0_DIFFM_AIN3 ((0 << 6) | (0 << 5) | (1 << 4))
57-
#define ADS1X1X_AIN1_DIFFM_AIN3 ((0 << 6) | (1 << 5) | (0 << 4))
58-
#define ADS1X1X_AIN2_DIFFM_AIN3 ((0 << 6) | (1 << 5) | (1 << 4))
59-
#define ADS1X1X_AIN0_SINGM ((1 << 6) | (0 << 5) | (0 << 4))
60-
#define ADS1X1X_AIN1_SINGM ((1 << 6) | (0 << 5) | (1 << 4))
61-
#define ADS1X1X_AIN2_SINGM ((1 << 6) | (1 << 5) | (0 << 4))
62-
#define ADS1X1X_AIN3_SINGM ((1 << 6) | (1 << 5) | (1 << 4))
46+
#define ADS1X1X_MUX_MASK ((1 << 6) | (1 << 5) | (1 << 4)) /**< Mask for MUX bits */
47+
#define ADS1X1X_AIN0_DIFFM_AIN1 ((0 << 6) | (0 << 5) | (0 << 4)) /**< Differential AIN0 - AIN1
48+
(default) */
49+
#define ADS1X1X_AIN0_DIFFM_AIN3 ((0 << 6) | (0 << 5) | (1 << 4)) /**< Differential AIN0 - AIN3 */
50+
#define ADS1X1X_AIN1_DIFFM_AIN3 ((0 << 6) | (1 << 5) | (0 << 4)) /**< Differential AIN1 - AIN3 */
51+
#define ADS1X1X_AIN2_DIFFM_AIN3 ((0 << 6) | (1 << 5) | (1 << 4)) /**< Differential AIN2 - AIN3 */
52+
#define ADS1X1X_AIN0_SINGM ((1 << 6) | (0 << 5) | (0 << 4)) /**< Single-ended AIN0 */
53+
#define ADS1X1X_AIN1_SINGM ((1 << 6) | (0 << 5) | (1 << 4)) /**< Single-ended AIN1 */
54+
#define ADS1X1X_AIN2_SINGM ((1 << 6) | (1 << 5) | (0 << 4)) /**< Single-ended AIN2 */
55+
#define ADS1X1X_AIN3_SINGM ((1 << 6) | (1 << 5) | (1 << 4)) /**< Single-ended AIN3 */
6356
/** @} */
6457

6558
/**
6659
* @name ADS101x/111x programmable gain
67-
*
6860
* Sets the full-scale range (max voltage value).
6961
* This has no effect on ADS1013 and ADS1113 (both use 2.048V FSR).
70-
*
7162
* @{
7263
*/
73-
#define ADS1X1X_PGA_MASK ((1 << 3) | (1 << 2) | (1 << 1))
74-
#define ADS1X1X_PGA_FSR_6V144 ((0 << 3) | (0 << 2) | (0 << 1))
75-
#define ADS1X1X_PGA_FSR_4V096 ((0 << 3) | (0 << 2) | (1 << 1))
76-
#define ADS1X1X_PGA_FSR_2V048 ((0 << 3) | (1 << 2) | (0 << 1))
77-
#define ADS1X1X_PGA_FSR_1V024 ((0 << 3) | (1 << 2) | (1 << 1))
78-
#define ADS1X1X_PGA_FSR_0V512 ((1 << 3) | (0 << 2) | (0 << 1))
79-
#define ADS1X1X_PGA_FSR_0V256 ((1 << 3) | (0 << 2) | (1 << 1))
64+
#define ADS1X1X_PGA_MASK ((1 << 3) | (1 << 2) | (1 << 1)) /**< Mask for PGA bits */
65+
#define ADS1X1X_PGA_FSR_6V144 ((0 << 3) | (0 << 2) | (0 << 1)) /**< +/-6.144V */
66+
#define ADS1X1X_PGA_FSR_4V096 ((0 << 3) | (0 << 2) | (1 << 1)) /**< +/-4.096V */
67+
#define ADS1X1X_PGA_FSR_2V048 ((0 << 3) | (1 << 2) | (0 << 1)) /**< +/-2.048V (default) */
68+
#define ADS1X1X_PGA_FSR_1V024 ((0 << 3) | (1 << 2) | (1 << 1)) /**< +/-1.024V */
69+
#define ADS1X1X_PGA_FSR_0V512 ((1 << 3) | (0 << 2) | (0 << 1)) /**< +/-0.512V */
70+
#define ADS1X1X_PGA_FSR_0V256 ((1 << 3) | (0 << 2) | (1 << 1)) /**< +/-0.256V */
8071
/** @} */
8172

8273
/**
8374
* @name ADS101x/111x operating modes
84-
*
85-
* MODE bit in the config register:
86-
* - @ref ADS1X1X_MODE_SINGLE : Single-shot (default), powers down after each conversion.
87-
* - @ref ADS1X1X_MODE_CONTINUOUS : Continuous conversions.
88-
*
89-
* @{9
75+
* MODE bit in the config register
76+
* @{
9077
*/
91-
#define ADS1X1X_MODE_MASK (1 << 0)
78+
#define ADS1X1X_MODE_MASK (1 << 0) /**< Mask for MODE bit */
9279
#define ADS1X1X_MODE_SINGLE (1 << 0) /**< Single-shot / power-down */
9380
#define ADS1X1X_MODE_CONTINUOUS (0 << 0) /**< Continuous conversion */
9481
/** @} */
9582

9683
/**
9784
* @name ADS101x/111x data rate settings
98-
*
9985
* Configures the data rate (samples per second).
10086
* Values differ between ADS101x and ADS111x families.
101-
*
10287
* @{
10388
*/
104-
#define ADS1X1X_DATAR_MASK ((1 << 7) | (1 << 6) | (1 << 5))
89+
#define ADS1X1X_DATAR_MASK ((1 << 7) | (1 << 6) | (1 << 5)) /**< Mask for data rate bits */
10590
#ifdef MODULE_ADS101X
106-
# define ADS1X1X_DATAR_128 ((0 << 7) | (0 << 6) | (0 << 5)) /**< 128 SPS */
107-
# define ADS1X1X_DATAR_250 ((0 << 7) | (0 << 6) | (1 << 5)) /**< 250 SPS */
108-
# define ADS1X1X_DATAR_490 ((0 << 7) | (1 << 6) | (0 << 5)) /**< 490 SPS */
109-
# define ADS1X1X_DATAR_920 ((0 << 7) | (1 << 6) | (1 << 5)) /**< 920 SPS */
110-
# define ADS1X1X_DATAR_1600 ((1 << 7) | (0 << 6) | (0 << 5)) /**< 1600 SPS (default) */
111-
# define ADS1X1X_DATAR_2400 ((1 << 7) | (0 << 6) | (1 << 5)) /**< 2400 SPS */
112-
# define ADS1X1X_DATAR_3300 ((1 << 7) | (1 << 6) | (0 << 5)) /**< 3300 SPS */
91+
# define ADS1X1X_DATAR_128 ((0 << 7) | (0 << 6) | (0 << 5)) /**< 128 SPS */
92+
# define ADS1X1X_DATAR_250 ((0 << 7) | (0 << 6) | (1 << 5)) /**< 250 SPS */
93+
# define ADS1X1X_DATAR_490 ((0 << 7) | (1 << 6) | (0 << 5)) /**< 490 SPS */
94+
# define ADS1X1X_DATAR_920 ((0 << 7) | (1 << 6) | (1 << 5)) /**< 920 SPS */
95+
# define ADS1X1X_DATAR_1600 ((1 << 7) | (0 << 6) | (0 << 5)) /**< 1600 SPS (default) */
96+
# define ADS1X1X_DATAR_2400 ((1 << 7) | (0 << 6) | (1 << 5)) /**< 2400 SPS */
97+
# define ADS1X1X_DATAR_3300 ((1 << 7) | (1 << 6) | (0 << 5)) /**< 3300 SPS */
11398
#elif defined(MODULE_ADS111X)
114-
# define ADS1X1X_DATAR_MASK ((1 << 7) | (1 << 6) | (1 << 5))
115-
# define ADS1X1X_DATAR_8 ((0 << 7) | (0 << 6) | (0 << 5)) /**< 8 SPS */
116-
# define ADS1X1X_DATAR_16 ((0 << 7) | (0 << 6) | (1 << 5)) /**< 16 SPS */
117-
# define ADS1X1X_DATAR_32 ((0 << 7) | (1 << 6) | (0 << 5)) /**< 32 SPS */
118-
# define ADS1X1X_DATAR_64 ((0 << 7) | (1 << 6) | (1 << 5)) /**< 64 SPS */
119-
# define ADS1X1X_DATAR_128 ((1 << 7) | (0 << 6) | (0 << 5)) /**< 128 SPS (default) */
120-
# define ADS1X1X_DATAR_250 ((1 << 7) | (0 << 6) | (1 << 5)) /**< 250 SPS */
121-
# define ADS1X1X_DATAR_475 ((1 << 7) | (1 << 6) | (0 << 5)) /**< 475 SPS */
122-
# define ADS1X1X_DATAR_860 ((1 << 7) | (1 << 6) | (1 << 5)) /**< 860 SPS */
99+
# define ADS1X1X_DATAR_8 ((0 << 7) | (0 << 6) | (0 << 5)) /**< 8 SPS */
100+
# define ADS1X1X_DATAR_16 ((0 << 7) | (0 << 6) | (1 << 5)) /**< 16 SPS */
101+
# define ADS1X1X_DATAR_32 ((0 << 7) | (1 << 6) | (0 << 5)) /**< 32 SPS */
102+
# define ADS1X1X_DATAR_64 ((0 << 7) | (1 << 6) | (1 << 5)) /**< 64 SPS */
103+
# define ADS1X1X_DATAR_128 ((1 << 7) | (0 << 6) | (0 << 5)) /**< 128 SPS (default) */
104+
# define ADS1X1X_DATAR_250 ((1 << 7) | (0 << 6) | (1 << 5)) /**< 250 SPS */
105+
# define ADS1X1X_DATAR_475 ((1 << 7) | (1 << 6) | (0 << 5)) /**< 475 SPS */
106+
# define ADS1X1X_DATAR_860 ((1 << 7) | (1 << 6) | (1 << 5)) /**< 860 SPS */
123107
#endif
124108
/** @} */
125109

126110
/**
127111
* @name Comparator mode
128-
*
129112
* Selects comparator operation
130-
*
131113
* @{
132114
*/
133-
#define ADS1X1X_COMP_MODE_MASK (1 << 4)
134-
#define ADS1X1X_COMP_MODE_TRADITIONAL (0 << 4) /**< Traditional comparator */
135-
#define ADS1X1X_COMP_MODE_WINDOW (1 << 4) /**< Window comparator */
115+
#define ADS1X1X_COMP_MODE_MASK (1 << 4) /**< Mask for COMP_MODE bit */
116+
#define ADS1X1X_COMP_MODE_TRADITIONAL (0 << 4) /**< Traditional comparator (default) */
117+
#define ADS1X1X_COMP_MODE_WINDOW (1 << 4) /**< Window comparator */
136118
/** @} */
137119

138120
/**
139121
* @name Comparator polarity
140-
*
141122
* Controls ALERT/RDY pin polarity
142-
*
143123
* @{
144124
*/
145-
#define ADS1X1X_COMP_POLARITY_MASK (1 << 3)
125+
#define ADS1X1X_COMP_POLARITY_MASK (1 << 3) /**< Mask for COMP_POLARITY bit */
146126
#define ADS1X1X_COMP_POLARITY_LOW (0 << 3) /**< Active low (default) */
147127
#define ADS1X1X_COMP_POLARITY_HIGH (1 << 3) /**< Active high */
148128
/** @} */
149129

150130
/**
151131
* @name Comparator latch
152-
*
153132
* Latching comparator output
154-
*
155133
* @{
156134
*/
157-
#define ADS1X1X_COMP_LATCH_MASK (1 << 2)
135+
#define ADS1X1X_COMP_LATCH_MASK (1 << 2) /**< Mask for COMP_LATCH bit */
158136
#define ADS1X1X_COMP_LATCH_DISABLE (0 << 2) /**< Non-latching (default) */
159137
#define ADS1X1X_COMP_LATCH_ENABLE (1 << 2) /**< Latching until read */
160138
/** @} */
161139

162140
/**
163141
* @name Comparator queue
164-
*
165142
* Configures comparator trigger queue
166-
*
167143
* @{
168144
*/
169-
#define ADS1X1X_COMP_QUEUE_MASK ((1 << 1) | (1 << 0))
170-
#define ADS1X1X_COMP_QUEUE_1 ((0 << 1) | (0 << 0)) /**< Assert after 1 conversion */
171-
#define ADS1X1X_COMP_QUEUE_2 ((0 << 1) | (1 << 0)) /**< Assert after 2 conversions */
172-
#define ADS1X1X_COMP_QUEUE_4 ((1 << 1) | (0 << 0)) /**< Assert after 4 conversions */
173-
#define ADS1X1X_COMP_QUEUE_DISABLE ((1 << 1) | (1 << 0)) /**< Disable comparator */
145+
#define ADS1X1X_COMP_QUEUE_MASK ((1 << 1) | (1 << 0)) /**< Mask for COMP_QUEUE bits */
146+
#define ADS1X1X_COMP_QUEUE_1 ((0 << 1) | (0 << 0)) /**< Assert after 1 conversion */
147+
#define ADS1X1X_COMP_QUEUE_2 ((0 << 1) | (1 << 0)) /**< Assert after 2 conversions */
148+
#define ADS1X1X_COMP_QUEUE_4 ((1 << 1) | (0 << 0)) /**< Assert after 4 conversions */
149+
#define ADS1X1X_COMP_QUEUE_DISABLE ((1 << 1) | (1 << 0)) /**< Disable comparator (default) */
174150
/** @} */
175151

176152
/**
177-
* @name ADS101x/111x alert configuration mask
178-
*
179-
* Mask for all alert-related configuration bits in the config register
153+
* @brief Mask for all alert-related configuration bits
180154
* (comparator mode, polarity, latch, queue).
181-
* This has no effect on ADS1113/1013.
182-
*
183-
* @{
184155
*/
185156
#define ADS1X1X_ALERT_MASK (ADS1X1X_COMP_QUEUE_MASK | ADS1X1X_COMP_LATCH_MASK | \
186157
ADS1X1X_COMP_POLARITY_MASK | ADS1X1X_COMP_MODE_MASK)
187-
/** @} */
188158

189159
/**
190160
* @brief Get the voltage reference for a given PGA setting
@@ -211,5 +181,3 @@ static inline int _ads1x1x_get_pga_voltage(uint8_t pga)
211181
#endif
212182

213183
/** @} */
214-
215-

‎drivers/ads1x1x/include/ads1x1x_params.h‎

Lines changed: 24 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,6 @@ extern "C" {
8787
# define ADS1X1X_BITS_RES (16)
8888
#endif
8989

90-
9190
/**
9291
* @def ADS1X1X_PARAM_PGA
9392
* @brief Default programmable gain amplifier configuration
@@ -97,17 +96,14 @@ extern "C" {
9796
#endif
9897

9998
/**
100-
* @def ADS1X1X_PARAM_DR
10199
* @brief Default data rate configuration
102100
*/
103101
#if MODULE_ADS101X
104102
# define ADS1X1X_PARAM_DATAR (ADS1X1X_DATAR_1600)
105-
#elif defined(MODULE_ADS111X)
103+
#elif defined(MODULE_ADS111X)
106104
# define ADS1X1X_PARAM_DATAR (ADS1X1X_DATAR_128)
107105
#endif
108106

109-
110-
111107
/**
112108
* @def ADS1X1X_PARAM_MODE
113109
* @brief Default operating mode
@@ -124,7 +120,6 @@ extern "C" {
124120
# define ADS1X1X_PARAM_COMP_MODE (ADS1X1X_COMP_MODE_TRADITIONAL)
125121
#endif
126122

127-
128123
/**
129124
* @def ADS1X1X_PARAM_COMP_POLARITY
130125
* @brief Default comparator polarity (No effect on ADS1113/1013)
@@ -149,29 +144,40 @@ extern "C" {
149144
# define ADS1X1X_PARAM_COMP_QUEUE (ADS1X1X_COMP_QUEUE_DISABLE)
150145
#endif
151146

152-
147+
/**
148+
* @def ADS1X1X_PARAMS
149+
* @brief Default ADS1X1X parameters structure
150+
*/
153151
#ifndef ADS1X1X_PARAMS
154-
#define ADS1X1X_PARAMS { .i2c = ADS1X1X_PARAM_I2C, \
155-
.addr = ADS1X1X_PARAM_ADDR, \
156-
.mux = ADS1X1X_PARAM_MUX, \
157-
.pga = ADS1X1X_PARAM_PGA, \
158-
.mode = ADS1X1X_PARAM_MODE, \
159-
.dr = ADS1X1X_PARAM_DATAR }
152+
#define ADS1X1X_PARAMS { .i2c = ADS1X1X_PARAM_I2C, \
153+
.addr = ADS1X1X_PARAM_ADDR, \
154+
.mux = ADS1X1X_PARAM_MUX, \
155+
.pga = ADS1X1X_PARAM_PGA, \
156+
.mode = ADS1X1X_PARAM_MODE, \
157+
.dr = ADS1X1X_PARAM_DATAR }
160158

161159
#endif
162160

161+
/**
162+
* @def ADS1X1X_ALERT_PARAMS
163+
* @brief Default ADS1X1X alert parameters structure
164+
*/
163165
#ifndef ADS1X1X_ALERT_PARAMS
164-
#define ADS1X1X_ALERT_PARAMS { .i2c = ADS1X1X_PARAM_I2C, \
165-
.addr = ADS1X1X_PARAM_ADDR, \
166-
.comp_mode = ADS1X1X_PARAM_COMP_MODE, \
166+
#define ADS1X1X_ALERT_PARAMS { .i2c = ADS1X1X_PARAM_I2C, \
167+
.addr = ADS1X1X_PARAM_ADDR, \
168+
.comp_mode = ADS1X1X_PARAM_COMP_MODE, \
167169
.comp_polarity = ADS1X1X_PARAM_COMP_POLARITY, \
168170
.comp_latch = ADS1X1X_PARAM_COMP_LATCH, \
169171
.comp_queue = ADS1X1X_PARAM_COMP_QUEUE, \
170-
.alert_pin = ADS1X1X_PARAM_ALERT_PIN, \
171-
.low_limit = ADS1X1X_PARAM_LOW_LIMIT, \
172+
.alert_pin = ADS1X1X_PARAM_ALERT_PIN, \
173+
.low_limit = ADS1X1X_PARAM_LOW_LIMIT, \
172174
.high_limit = ADS1X1X_PARAM_HIGH_LIMIT }
173175
#endif
174176

177+
/**
178+
* @def ADS1X1X_SAUL_INFO
179+
* @brief Additional SAUL registry information
180+
*/
175181
#ifndef ADS1X1X_SAUL_INFO
176182
#define ADS1X1X_SAUL_INFO { .name = "ads1x1x" }
177183
#endif

‎drivers/include/ads1x1x.h‎

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,6 @@ extern "C" {
3232
#include "periph/i2c.h"
3333
#include "periph/gpio.h"
3434

35-
3635
/**
3736
* @brief Named return values
3837
*/
@@ -45,7 +44,6 @@ enum {
4544
ADS1X1X_GPIO_ERROR = -5 /**< GPIO error */
4645
};
4746

48-
4947
/**
5048
* @brief ADS101x/111x params
5149
*/
@@ -73,15 +71,13 @@ typedef struct ads1x1x_alert_params {
7371
int16_t high_limit; /**< alert high value */
7472
} ads1x1x_alert_params_t;
7573

76-
7774
/**
7875
* @brief ADS101x/111x device descriptor
7976
*/
8077
typedef struct ads1x1x {
8178
ads1x1x_params_t params; /**< device driver configuration */
8279
} ads1x1x_t;
8380

84-
8581
/**
8682
* @brief ADS101x/111x alert callback
8783
*/
@@ -134,7 +130,7 @@ int ads1x1x_alert_init(ads1x1x_alert_t *dev,
134130
* Gain settings have no effect on ADS1013 and ADS1113.
135131
*
136132
* @param[in] dev device descriptor
137-
* @param[in] mux_gain mux and gain boolean values
133+
* @param[in] mux mux bits
138134
*
139135
* @return zero on successful read, non zero on error
140136
*/

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