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cpu/riscv_common: Add periph xh3irq support

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# fixup! cpu/riscv_common: Add periph xh3irq support

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# fixup! fixup! cpu/riscv_common: Add periph xh3irq support

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# fixup! fixup! fixup! cpu/riscv_common: Add periph xh3irq support

Author: AnnsAnns

cpu/riscv_common/include/xh3irq.h

@@ -7,8 +7,9 @@
 #pragma once
 
 #include <stdio.h>
-#include "cpu_conf.h"
+
 #include "panic.h"
+#include "cpu_conf.h"
 
 /**
  * @ingroup     cpu_riscv_common
@@ -29,6 +30,32 @@ extern "C" {
  */
 extern const void *vector_cpu[CPU_IRQ_NUMOF];
 
+/**
+ * Hazard3 has internal registers to individually filter which
+ * external IRQs appear in meip. When meip is 1,
+ * this indicates there is at least one external interrupt
+ * which is asserted (hence pending in mieipa), enabled in meiea,
+ * and of priority greater than or equal to the current
+ * preemption level in meicontext.preempt.
+ */
+#define MEIP_OFFSET 11
+/* Mask to extract the MEIP bit from MIP/MISE */
+#define MEIP_MASK 0x1
+/**
+ * Index of the highest-priority active external interrupt.
+ * Zero when no external interrupts with sufficient priority
+ * are both pending and enabled
+ */
+#define MEINEXT_IRQ_OFFSET 2
+/** Mask to extract the IRQ number from MEINEXT */
+#define MEINEXT_MASK 0x1FF
+/** XH3IRQ Interrupt arrays have a window to access the IRQ bits */
+#define INTERRUPT_ARRAY_MASK_OFFSET 16
+
+/**
+ * @brief  Check if there are any pending interrupts
+ * @return 1 if there are pending interrupts, 0 otherwise
+ */
 uint32_t xh3irq_has_pending(void);
 void xh3irq_handler(void);
 

cpu/riscv_common/irq_arch.c

@@ -98,27 +98,45 @@ __attribute((used)) static void handle_trap(uword_t mcause)
 
 #ifdef DEVELHELP
     printf("Trap: mcause=0x%" PRIx32 " mepc=0x%lx mtval=0x%lx\n",
-           (uint32_t)mcause, read_csr(mepc), read_csr(mtval));
+          (uint32_t)mcause, read_csr(mepc), read_csr(mtval));
 
+    /* See https://riscv.github.io/riscv-isa-manual/snapshot/privileged/#mcause */
     if ((mcause & ~MCAUSE_INT) <= 0xb) {
         const char *error_messages[] = {
-            "Instruction alignment: Does not occur on RP2350, because 16-bit compressed instructions are implemented, and it is impossible to jump to a byte-aligned address.",
-            "Instruction fetch fault: Attempted to fetch from an address that does not support instruction fetch (like APB/AHB peripherals on RP2350), or lacks PMP execute permission, or is forbidden by ACCESSCTRL, or returned a fault from the memory device itself.",
-            "Illegal instruction: Encountered an instruction that was not a valid RISC-V opcode implemented by this processor, or attempted to access a nonexistent CSR, or attempted to execute a privileged instruction or access a privileged CSR without sufficient privilege.",
-            "Breakpoint: An ebreak or c.ebreak instruction was executed, and no external debug host caught it (DCSR.EBREAKM or DCSR.EBREAKU was not set).",
-            "Load alignment: Attempted to load from an address that was not a multiple of access size.",
-            "Load fault: Attempted to load from an address that does not exist, or lacks PMP read permissions, or is forbidden by ACCESSCTRL, or returned a fault from a peripheral.",
-            "Store/AMO alignment: Attempted to write to an address that was not a multiple of access size.",
-            "Store/AMO fault: Attempted to write to an address that does not exist, or lacks PMP write permissions, or is forbidden by ACCESSCTRL, or returned a fault from a peripheral. Also raised when attempting an AMO on an address that does not support AHB5 exclusives.",
-            "An ecall instruction was executed in U-mode.",
-            NULL, /* 0x9 - not defined */
-            NULL, /* 0xa - not defined */
-            "An ecall instruction was executed in M-mode."
+            "Instruction address misaligned",
+            "Instruction access fault",
+            "Illegal instruction",
+            "Breakpoint",
+            "Load address misaligned",
+            "Load access fault",
+            "Store/AMO address misaligned",
+            "Store/AMO access fault",
+            "Environment call from U-mode",
+            "Environment call from S-mode",
+            NULL,
+            "Environment call from M-mode",
+            "Instruction page fault",
+            "Load page fault",
+            NULL,
+            "Store/AMO page fault",
+            "Double trap",
+            NULL,
+            "Software check",
+            "Hardware error"
         };
 
         uword_t cause_code = mcause & ~MCAUSE_INT;
-        if (cause_code <= 0xb && error_messages[cause_code] != NULL) {
-            printf("Error 0x%lx: %s\n", cause_code, error_messages[cause_code]);
+        if (cause_code <= (ARRAY_SIZE(error_messages) - 1)) {
+            if (error_messages[cause_code] != NULL) {
+                printf("Machine Cause Error 0x%lx: %s\n",
+                        cause_code, error_messages[cause_code]
+                );
+            } else {
+                printf("Machine Cause indicates that 0x%lx"
+                        " is a reserved or custom cause code\n",
+                        cause_code
+                );
+            }
         }
     }
 #endif
@@ -156,8 +174,8 @@ __attribute((used)) static void handle_trap(uword_t mcause)
     }
     else {
         switch (trap) {
-        case CAUSE_USER_ECALL:    /* ECALL from user mode */
-        case CAUSE_MACHINE_ECALL: /* ECALL from machine mode */
+        case CAUSE_USER_ECALL:      /* ECALL from user mode */
+        case CAUSE_MACHINE_ECALL:   /* ECALL from machine mode */
         {
             /* TODO: get the ecall arguments */
             sched_context_switch_request = 1;

cpu/riscv_common/periph/xh3irq.c

@@ -2,29 +2,49 @@
 #include <stdio.h>
 
 uint32_t xh3irq_has_pending(void) {
-    // Get MEIP at 0x344 which is the external interrupt pending bit
-    uint32_t meip = (read_csr(0x344) >> 11) & 0x1;
+    /*
+     * Get MEIP which is the external interrupt pending bit
+     * from the Machine Interrupt Pending Register address
+     */
+    uint32_t meip = (read_csr(0x344) >> MEIP_OFFSET) & MEIP_MASK;
 
     return (meip != 0);
 }
 
 void xh3irq_handler(void) {
-    /* Get MEINEXT at 0xbe4 which is the next highest interrupt to handle (Bit 2-10) */
-    /* This will also automagically clear the interrupt (See 3.8.6.1.2.) */
-    uint32_t meinext = (read_csr(0xbe4) >> 2) & 0x1ff;
+    /*
+     * Get MEINEXT at 0xbe4 which is the next highest interrupt to handle (Bit 2-10).
+     * This will also automagically clear the interrupt (See 3.8.6.1.2.)
+     *
+     * Contains the index of the highest-priority external interrupt
+     * which is both asserted in meipa and enabled in meiea, left-
+     * shifted by 2 so that it can be used to index an array of 32-bit
+     * function pointers. If there is no such interrupt, the MSB is set.
+     */
+    uint32_t meinext = (read_csr(0xBE4) >> MEINEXT_IRQ_OFFSET) & MEINEXT_MASK;
 
     void (*isr)(void) = (void (*)(void))vector_cpu[meinext];
+#ifdef DEVELHELP
     printf("Calling isr %p for irq %ld\n", isr, meinext);
+#endif
     isr();
 }
 
 void _meiea_set_req_bit(uint32_t irq_no, uint32_t bit_val) {
-    uint32_t index = irq_no / 16;
-    uint32_t mask = bit_val << (irq_no % 16);
+    uint32_t index = irq_no / INTERRUPT_ARRAY_MASK_OFFSET;
+    uint32_t mask = bit_val << (irq_no % INTERRUPT_ARRAY_MASK_OFFSET);
 
+    /*
+     * 0xbe0 is the external interrupt enable array.
+     * The array contains a read-write bit for each external interrupt request:
+     * a 1 bit indicates that interrupt is currently enabled.
+     * There are up to 512 external interrupts.
+     * The upper half of this register contains a 16-bit window into the full
+     * 512-bit vector. The window is indexed by the 5 LSBs of the write data.
+     */
     __asm__ volatile(
         "csrs 0xbe0, %0\n"
-        : : "r"(index | (mask << 16))
+        : : "r"(index | (mask << INTERRUPT_ARRAY_MASK_OFFSET))
 
     );
 }
@@ -41,11 +61,15 @@ void xh3irq_disable_irq(uint32_t irq_no)
 
 void xh3irq_force_irq(uint32_t irq_no)
 {
-    uint32_t index = irq_no / 16;
-    uint32_t mask = 1u << (irq_no % 16);
+    uint32_t index = irq_no / INTERRUPT_ARRAY_MASK_OFFSET;
+    uint32_t mask = 1u << (irq_no % INTERRUPT_ARRAY_MASK_OFFSET);
 
+    /**
+     * 0xbe2 is the external interrupt force array.
+     * See _meiea_set_req_bit / 0xbe0 for more details.
+     */
     __asm__ volatile(
         "csrs 0xbe2, %0\n"
-        : : "r"(index | (mask << 16))
+        : : "r"(index | (mask << INTERRUPT_ARRAY_MASK_OFFSET))
     );
 }