cpu/rp2350: move to new uart

AnnsAnns · AnnsAnns · commit c5dd279d5589 · 2025-10-08T15:12:21.000+02:00
diff --git a/cpu/riscv_common/irq_arch.c b/cpu/riscv_common/irq_arch.c
@@ -30,7 +30,6 @@
 #include "sched.h"
 #include "plic.h"
 #include "clic.h"
-#include "xh3irq.h"
 #include "architecture.h"
 
 #if MODULE_PERIPH_XH3IRQ || DOXYGEN
diff --git a/cpu/rp2350_riscv/cpu.c b/cpu/rp2350_riscv/cpu.c
@@ -23,8 +23,6 @@
 #include "periph/uart.h"
 #include "periph_conf.h"
 
-#include "stdio_uart.h"
-#include <stdio.h>
 #include <sys/unistd.h>
 
 void gpio_reset(void)
@@ -38,12 +36,6 @@ void gpio_reset(void)
  */
 void cpu_init(void)
 {
-    riscv_init();
-
-    uint32_t ra_register = 0;
-
-    __asm__ volatile ("mv %0, ra" : "=r"(ra_register));
-
     /* Reset GPIO state */
     gpio_reset();
 
@@ -53,18 +45,15 @@ void cpu_init(void)
     /* initialize the CPU clock */
     cpu_clock_init();
 
+    /* initialize the RISC-V core */
+    riscv_init();
+
     /* initialize the early peripherals */
     early_init();
 
     /* trigger static peripheral initialization */
     periph_init();
 
+    /* initialize the board */
     board_init();
-
-    xosc_sleep(1000);
-    printf("Enabling IRQ 50\n");
-
-    printf("ra register at start of cpu_init: 0x%lx\n", ra_register);
-
-    __asm__ volatile ("nop");
 }
diff --git a/cpu/rp2350_riscv/include/cpu_conf.h b/cpu/rp2350_riscv/include/cpu_conf.h
@@ -24,64 +24,6 @@ extern "C" {
 #define CPU_DEFAULT_IRQ_PRIO 1u
 #define CPU_IRQ_NUMOF 52u
 
-/**
- * @brief Interrupt numbers for RP2350 RISC-V
- */
-typedef enum {
-    TIMER0_IRQ_0_IRQn = 0,      /**< Timer 0 interrupt 0 */
-    TIMER0_IRQ_1_IRQn = 1,      /**< Timer 0 interrupt 1 */
-    TIMER0_IRQ_2_IRQn = 2,      /**< Timer 0 interrupt 2 */
-    TIMER0_IRQ_3_IRQn = 3,      /**< Timer 0 interrupt 3 */
-    TIMER1_IRQ_0_IRQn = 4,      /**< Timer 1 interrupt 0 */
-    TIMER1_IRQ_1_IRQn = 5,      /**< Timer 1 interrupt 1 */
-    TIMER1_IRQ_2_IRQn = 6,      /**< Timer 1 interrupt 2 */
-    TIMER1_IRQ_3_IRQn = 7,      /**< Timer 1 interrupt 3 */
-    PWM_IRQ_WRAP_0_IRQn = 8,    /**< PWM wrap interrupt 0 */
-    PWM_IRQ_WRAP_1_IRQn = 9,    /**< PWM wrap interrupt 1 */
-    DMA_IRQ_0_IRQn = 10,        /**< DMA interrupt 0 */
-    DMA_IRQ_1_IRQn = 11,        /**< DMA interrupt 1 */
-    DMA_IRQ_2_IRQn = 12,        /**< DMA interrupt 2 */
-    DMA_IRQ_3_IRQn = 13,        /**< DMA interrupt 3 */
-    USBCTRL_IRQ_IRQn = 14,      /**< USB controller interrupt */
-    PIO0_IRQ_0_IRQn = 15,       /**< PIO 0 interrupt 0 */
-    PIO0_IRQ_1_IRQn = 16,       /**< PIO 0 interrupt 1 */
-    PIO1_IRQ_0_IRQn = 17,       /**< PIO 1 interrupt 0 */
-    PIO1_IRQ_1_IRQn = 18,       /**< PIO 1 interrupt 1 */
-    PIO2_IRQ_0_IRQn = 19,       /**< PIO 2 interrupt 0 */
-    PIO2_IRQ_1_IRQn = 20,       /**< PIO 2 interrupt 1 */
-    IO_IRQ_BANK0_IRQn = 21,     /**< IO bank 0 interrupt */
-    IO_IRQ_BANK0_NS_IRQn = 22,  /**< IO bank 0 non-secure interrupt */
-    IO_IRQ_QSPI_IRQn = 23,      /**< IO QSPI interrupt */
-    IO_IRQ_QSPI_NS_IRQn = 24,   /**< IO QSPI non-secure interrupt */
-    SIO_IRQ_FIFO_IRQn = 25,     /**< SIO FIFO interrupt */
-    SIO_IRQ_BELL_IRQn = 26,     /**< SIO bell interrupt */
-    SIO_IRQ_FIFO_NS_IRQn = 27,  /**< SIO FIFO non-secure interrupt */
-    SIO_IRQ_BELL_NS_IRQn = 28,  /**< SIO bell non-secure interrupt */
-    SIO_IRQ_MTIMECMP_IRQn = 29, /**< SIO MTIMECMP interrupt */
-    CLOCKS_IRQ_IRQn = 30,       /**< Clocks interrupt */
-    SPI0_IRQ_IRQn = 31,         /**< SPI 0 interrupt */
-    SPI1_IRQ_IRQn = 32,         /**< SPI 1 interrupt */
-    UART0_IRQ_IRQn = 33,        /**< UART 0 interrupt */
-    UART1_IRQ_IRQn = 34,        /**< UART 1 interrupt */
-    ADC_IRQ_FIFO_IRQn = 35,     /**< ADC FIFO interrupt */
-    I2C0_IRQ_IRQn = 36,         /**< I2C 0 interrupt */
-    I2C1_IRQ_IRQn = 37,         /**< I2C 1 interrupt */
-    OTP_IRQ_IRQn = 38,          /**< OTP interrupt */
-    TRNG_IRQ_IRQn = 39,         /**< TRNG interrupt */
-    PROC0_IRQ_CTI_IRQn = 40,    /**< Processor 0 CTI interrupt */
-    PROC1_IRQ_CTI_IRQn = 41,    /**< Processor 1 CTI interrupt */
-    PLL_SYS_IRQ_IRQn = 42,      /**< PLL SYS interrupt */
-    PLL_USB_IRQ_IRQn = 43,      /**< PLL USB interrupt */
-    POWMAN_IRQ_POW_IRQn = 44,   /**< Power manager power interrupt */
-    POWMAN_IRQ_TIMER_IRQn = 45, /**< Power manager timer interrupt */
-    SPAREIRQ_IRQ_0_IRQn = 46,   /**< Spare interrupt 0 */
-    SPAREIRQ_IRQ_1_IRQn = 47,   /**< Spare interrupt 1 */
-    SPAREIRQ_IRQ_2_IRQn = 48,   /**< Spare interrupt 2 */
-    SPAREIRQ_IRQ_3_IRQn = 49,   /**< Spare interrupt 3 */
-    SPAREIRQ_IRQ_4_IRQn = 50,   /**< Spare interrupt 4 */
-    SPAREIRQ_IRQ_5_IRQn = 51    /**< Spare interrupt 5 */
-} IRQn_Type;
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/cpu/rp2350_riscv/periph/uart.c b/cpu/rp2350_riscv/periph/uart.c
@@ -5,7 +5,7 @@
  */
 
 /**
- * @ingroup         cpu_rp2350_riscv
+ * @ingroup         cpu_rp2350
  * @{
  *
  * @file
@@ -18,69 +18,214 @@
 
 #include "periph_cpu.h"
 
-int uart_init(uart_t uart, uint32_t baud, uart_rx_cb_t rx_cb, void *arg) {
-    (void)uart;
-    (void)baud;
-    (void)rx_cb;
-    (void)arg;
-    /* Set the UART pins to the correct function */
-    IO_BANK0->GPIO0_CTRL = FUNCTION_SELECT_UART;
-    IO_BANK0->GPIO1_CTRL = FUNCTION_SELECT_UART;
-    /* Clear the ISO bits */
-    atomic_clear(&PADS_BANK0->GPIO0, PADS_BANK0_ISO_BITS);
-    atomic_clear(&PADS_BANK0->GPIO1, PADS_BANK0_ISO_BITS);
-    /* Set IE bit for gpio1 */
-    PADS_BANK0->GPIO1 = PADS_BANK0->GPIO1 | PADS_BANK0_GPIO0_IE_BITS;
+#include "regs/uart.h"
+#include <RP2350.h>
 
-    /* We reset UART0 here, so we can be sure it is in a known state */
-    reset_component(RESET_UART0, RESET_UART0);
+#define ENABLE_DEBUG 0
+#include "debug.h"
+
+#include "xh3irq.h"
+
+#include "board.h"
+
+static uart_isr_ctx_t ctx[UART_NUMOF];
 
-    UART0->UARTIBRD = IBRD;
-    UART0->UARTFBRD = FBRD;
-    uart_mode(0, 8, UART_PARITY_NONE, 1);
-    return 0;
+/* back up values of registers used during uart_poweroff() / uart_poweron() */
+static uint32_t uartibrd;
+static uint32_t uartfbrd;
+static uint32_t uartlcr_h;
+static uint32_t uartcr;
+
+/** Pico1 uart uses non-sdk conform defines
+ * @todo Change Pico1 defines if I ever get around to it
+ */
+#define UART0_UARTIMSC_RXIM_Msk (UART_UARTIMSC_RXIM_BITS)
+
+void _irq_enable(uart_t uart) {
+    UART0_Type *dev = uart_config[uart].dev;
+    /* We set the UART Receive Interrupt Mask (Bit 4) [See p979 UART 12.1]*/
+    dev->UARTIMSC = UART0_UARTIMSC_RXIM_Msk;
+    /* Enable the IRQ in the NVIC */
+    xh3irq_enable_irq(uart_config[uart].irqn);
 }
 
 int uart_mode(uart_t uart, uart_data_bits_t data_bits, uart_parity_t parity,
-    uart_stop_bits_t stop_bits) {
-    (void)uart;
+              uart_stop_bits_t stop_bits) {
+    assert((unsigned)uart < UART_NUMOF);
+    UART0_Type *dev = uart_config[uart].dev;
+
     (void)data_bits;
     (void)stop_bits;
-    atomic_clear(&UART0->UARTCR, UART_UARTCR_UARTEN_BITS | UART_UARTCR_RXE_BITS |
-        UART_UARTCR_TXE_BITS);
+
+    /* Disable the UART before changing the mode */
+    atomic_clear(&dev->UARTCR, UART_UARTCR_UARTEN_BITS | UART_UARTCR_RXE_BITS |
+                                   UART_UARTCR_TXE_BITS);
 
     /* Set the data bits, parity, and stop bits
      * Set to 8 bits (0b11) based on Table 1035 page 976
+     * @todo allow different data bits
      */
-    UART0->UARTLCR_H = 0b11 << 5;
+    dev->UARTLCR_H = 0b11 << 5;
 
     switch (parity) {
-        case UART_PARITY_NONE:
+    case UART_PARITY_NONE:
         break;
-        default:
+    // case UART_PARITY_EVEN:
+    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_EPS_Msk | UART0_UARTLCR_H_PEN_Msk);
+    //     break;
+    // case UART_PARITY_ODD:
+    //     io_reg_atomic_set(&dev->UARTLCR_H, UART0_UARTLCR_H_PEN_Msk);
+    //     break;
+    default:
         return UART_NOMODE;
     }
 
-    UART0->UARTCR = UART_UARTCR_TXE_BITS | UART_UARTCR_UARTEN_BITS;
+    dev->UARTCR = UART_UARTCR_TXE_BITS | UART_UARTCR_UARTEN_BITS | UART_UARTCR_RXE_BITS;
+
+    return UART_OK;
+}
+
+static void _reset_uart(uart_t uart) {
+    switch (uart) {
+    case 0:
+        /* We reset UART0 here, so we can be sure it is in a known state */
+        reset_component(RESET_UART0, RESET_UART0);
+        break;
+    case 1:
+        /* We reset UART1 here, so we can be sure it is in a known state */
+        reset_component(RESET_UART1, RESET_UART1);
+        break;
+    default:
+        break;
+    }
+}
+
+void uart_init_pins(uart_t uart) {
+    assert((unsigned)uart < UART_NUMOF);
+    UART0_Type *dev = uart_config[uart].dev;
+
+    /* Set the UART pins to the correct function */
+    *(uint32_t *)calculate_gpio_io_ctrl_register_addr(uart_config[uart].tx_pin) = FUNCTION_SELECT_UART;
+    *(uint32_t *)calculate_gpio_io_ctrl_register_addr(uart_config[uart].rx_pin) = FUNCTION_SELECT_UART;
+    /* Clear the ISO bits */
+    atomic_clear((uint32_t *)calculate_gpio_pad_register_addr(uart_config[uart].tx_pin), PADS_BANK0_ISO_BITS);
+    atomic_clear((uint32_t *)calculate_gpio_pad_register_addr(uart_config[uart].rx_pin), PADS_BANK0_ISO_BITS);
+
+    /* Set Input Enable Flag  */
+    atomic_set((uint32_t *)calculate_gpio_pad_register_addr(uart_config[uart].rx_pin), PADS_BANK0_GPIO0_IE_BITS);
+
+    /* We reset UART0 here, so we can be sure it is in a known state */
+    _reset_uart(uart);
+
+    dev->UARTIBRD = IBRD;
+    dev->UARTFBRD = FBRD;
+}
+
+int uart_init(uart_t uart, uint32_t baud, uart_rx_cb_t rx_cb, void *arg) {
+    (void)baud;
+
+    if (uart >= UART_NUMOF) {
+        return UART_NODEV;
+    }
+
+    UART0_Type *dev = uart_config[uart].dev;
+    ctx[uart].rx_cb = rx_cb;
+    ctx[uart].arg = arg;
+
+    uart_init_pins(uart);
+
+    if (uart_mode(uart, UART_DATA_BITS_8, UART_PARITY_NONE, UART_STOP_BITS_1) != UART_OK) {
+        return UART_NOMODE;
+    }
+
+    /* enable RX and IRQs, if needed */
+    if (rx_cb != NULL) {
+        _irq_enable(uart);
+        /* clear any pending data and IRQ to avoid receiving a garbage char */
+        uint32_t status = dev->UARTRIS;
+        dev->UARTICR = status;
+        (void)dev->UARTDR;
+        atomic_set(&dev->UARTCR, UART_UARTCR_RXE_BITS);
+    }
 
     return UART_OK;
 }
 
 void uart_write(uart_t uart, const uint8_t *data, size_t len) {
-    (void)uart;
+    UART0_Type *dev = uart_config[uart].dev;
     for (size_t i = 0; i < len; i++) {
-        UART0->UARTDR = data[i];
+        dev->UARTDR = data[i];
         /* Wait until the TX FIFO is empty before sending the next byte */
-        while (!(UART0->UARTFR & UART_UARTFR_TXFE_BITS)) {
+        while (!(dev->UARTFR & UART_UARTFR_TXFE_BITS)) {
         }
     }
 }
 
 void uart_poweron(uart_t uart) {
-    (void)uart;
+    assert((unsigned)uart < UART_NUMOF);
+    /* Get into a save state where we know whats up */
+    _reset_uart(uart);
+    UART0_Type *dev = uart_config[uart].dev;
+    /* Restore config from registers */
+    dev->UARTIBRD = uartibrd;
+    dev->UARTFBRD = uartfbrd;
+    dev->UARTLCR_H = uartlcr_h;
+    dev->UARTCR = uartcr;
+    /* restore IRQs, if needed */
+    if (ctx[uart].rx_cb != NULL) {
+        _irq_enable(uart);
+    }
+    uart_init_pins(uart);
+}
+
+void uart_deinit_pins(uart_t uart) {
+    assert((unsigned)uart < UART_NUMOF);
+    /* @TODO */
+    /* gpio_reset_all_config(uart_config[uart].tx_pin); */
+    SIO->GPIO_OE_CLR = 1LU << uart_config[uart].tx_pin;
+    if (ctx[uart].rx_cb) {
+        /* gpio_reset_all_config(uart_config[uart].rx_pin); */
+    }
 }
+
 void uart_poweroff(uart_t uart) {
-    (void)uart;
+    assert((unsigned)uart < UART_NUMOF);
+    UART0_Type *dev = uart_config[uart].dev;
+    /* backup configuration registers */
+    uartibrd = dev->UARTIBRD;
+    uartfbrd = dev->UARTFBRD;
+    uartlcr_h = dev->UARTLCR_H;
+    uartcr = dev->UARTCR;
+    /* disconnect GPIOs and power off peripheral */
+    uart_deinit_pins(uart);
+    _reset_uart(uart);
+}
+
+void isr_handler(uint8_t num) {
+    UART0_Type *dev = uart_config[num].dev;
+
+    uint32_t status = dev->UARTMIS;
+    dev->UARTICR = status;
+
+    if (status & UART_UARTMIS_RXMIS_BITS) {
+        uint32_t data = dev->UARTDR;
+        // if (data & (UART0_UARTDR_BE_Msk | UART0_UARTDR_PE_Msk | UART0_UARTDR_FE_Msk)) {
+        //     DEBUG_PUTS("[rpx0xx] uart RX error (parity, break, or framing error");
+        // }
+        // else {
+        printf("UART%d received: %c\n", num, (char)(data & 0xFF));
+        ctx[num].rx_cb(ctx[num].arg, (uint8_t)data);
+        // }
+    }
+}
+
+/** Overwrites the WEAK_DEFAULT isr_uart0 */
+void isr_uart0(void) {
+    isr_handler(0);
+}
+
+void isr_uart1(void) {
+    isr_handler(1);
 }
 
 /** @} */
