From 2aa3b6c1e9f49d309772dc2e6b6d27c477a9e087 Mon Sep 17 00:00:00 2001 From: DannyCato Date: Sun, 29 Mar 2026 12:06:51 -0400 Subject: [PATCH 1/5] Adding SDRAM HAL .c files --- libs/HALf4/src/stm32f4xx_hal_sdram.c | 1313 ++++++++++++++++++++++ libs/HALf4/src/stm32f4xx_ll_fmc.c | 1497 ++++++++++++++++++++++++++ 2 files changed, 2810 insertions(+) create mode 100644 libs/HALf4/src/stm32f4xx_hal_sdram.c create mode 100644 libs/HALf4/src/stm32f4xx_ll_fmc.c diff --git a/libs/HALf4/src/stm32f4xx_hal_sdram.c b/libs/HALf4/src/stm32f4xx_hal_sdram.c new file mode 100644 index 00000000..da5226fa --- /dev/null +++ b/libs/HALf4/src/stm32f4xx_hal_sdram.c @@ -0,0 +1,1313 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_sdram.c + * @author MCD Application Team + * @brief SDRAM HAL module driver. + * This file provides a generic firmware to drive SDRAM memories mounted + * as external device. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a generic layered driver which contains a set of APIs used to + control SDRAM memories. It uses the FMC layer functions to interface + with SDRAM devices. + The following sequence should be followed to configure the FMC to interface + with SDRAM memories: + + (#) Declare a SDRAM_HandleTypeDef handle structure, for example: + SDRAM_HandleTypeDef hsdram + + (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed + values of the structure member. + + (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SDRAM device + + (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: + FMC_SDRAM_TimingTypeDef Timing; + and fill its fields with the allowed values of the structure member. + + (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function + performs the following sequence: + + (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() + (##) Control register configuration using the FMC SDRAM interface function + FMC_SDRAM_Init() + (##) Timing register configuration using the FMC SDRAM interface function + FMC_SDRAM_Timing_Init() + (##) Program the SDRAM external device by applying its initialization sequence + according to the device plugged in your hardware. This step is mandatory + for accessing the SDRAM device. + + (#) At this stage you can perform read/write accesses from/to the memory connected + to the SDRAM Bank. You can perform either polling or DMA transfer using the + following APIs: + (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access + (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer + + (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ + HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or + the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM + device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef + structure. + + (#) You can continuously monitor the SDRAM device HAL state by calling the function + HAL_SDRAM_GetState() + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_SDRAM_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) MspInitCallback : SDRAM MspInit. + (+) MspDeInitCallback : SDRAM MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default + weak (overridden) function. It allows to reset following callbacks: + (+) MspInitCallback : SDRAM MspInit. + (+) MspDeInitCallback : SDRAM MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET + all callbacks are reset to the corresponding legacy weak (overridden) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init + and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit + or HAL_SDRAM_Init function. + + When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (overridden) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +#if defined(FMC_Bank5_6) + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + +/** @defgroup SDRAM SDRAM + * @brief SDRAM driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ +static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma); +static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma); +static void SDRAM_DMAError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions + * @{ + */ + +/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### SDRAM Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize + the SDRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Performs the SDRAM device initialization sequence. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param Timing Pointer to SDRAM control timing structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) +{ + /* Check the SDRAM handle parameter */ + if (hsdram == NULL) + { + return HAL_ERROR; + } + + if (hsdram->State == HAL_SDRAM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsdram->Lock = HAL_UNLOCKED; +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + if (hsdram->MspInitCallback == NULL) + { + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + } + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + + /* Init the low level hardware */ + hsdram->MspInitCallback(hsdram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspInit(hsdram); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + } + + /* Initialize the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Initialize SDRAM control Interface */ + (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); + + /* Initialize SDRAM timing Interface */ + (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Perform the SDRAM device initialization sequence. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) +{ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + if (hsdram->MspDeInitCallback == NULL) + { + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + } + + /* DeInit the low level hardware */ + hsdram->MspDeInitCallback(hsdram); +#else + /* Initialize the low level hardware (MSP) */ + HAL_SDRAM_MspDeInit(hsdram); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + + /* Configure the SDRAM registers with their reset values */ + (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); + + /* Reset the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + + return HAL_OK; +} + +/** + * @brief SDRAM MSP Init. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_MspInit could be implemented in the user file + */ +} + +/** + * @brief SDRAM MSP DeInit. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function handles SDRAM refresh error interrupt request. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) +{ + /* Check SDRAM interrupt Rising edge flag */ + if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) + { + /* SDRAM refresh error interrupt callback */ +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->RefreshErrorCallback(hsdram); +#else + HAL_SDRAM_RefreshErrorCallback(hsdram); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + + /* Clear SDRAM refresh error interrupt pending bit */ + __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); + } +} + +/** + * @brief SDRAM Refresh error callback. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval None + */ +__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsdram); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file + */ +} + +/** + * @brief DMA transfer complete error callback. + * @param hdma DMA handle + * @retval None + */ +__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hdma); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions + * + @verbatim + ============================================================================== + ##### SDRAM Input and Output functions ##### + ============================================================================== + [..] + This section provides functions allowing to use and control the SDRAM memory + +@endverbatim + * @{ + */ + +/** + * @brief Reads 8-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; + uint8_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from source */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *(__IO uint8_t *)pSdramAddress; + pdestbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 8-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; + uint8_t *psrcbuff = pSrcBuffer; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *(__IO uint8_t *)pSdramAddress = *psrcbuff; + psrcbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 16-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *pSdramAddress = pAddress; + uint16_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size >= 2U ; size -= 2U) + { + *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); + pdestbuff++; + *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U); + pdestbuff++; + pSdramAddress++; + } + + /* Read last 16-bits if size is not 32-bits multiple */ + if ((BufferSize % 2U) != 0U) + { + *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 16-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *psdramaddress = pAddress; + uint16_t *psrcbuff = pSrcBuffer; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size >= 2U ; size -= 2U) + { + *psdramaddress = (uint32_t)(*psrcbuff); + psrcbuff++; + *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U); + psrcbuff++; + psdramaddress++; + } + + /* Write last 16-bits if size is not 32-bits multiple */ + if ((BufferSize % 2U) != 0U) + { + *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U); + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads 32-bit data buffer from the SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; + uint32_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from source */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *(__IO uint32_t *)pSdramAddress; + pdestbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Writes 32-bit data buffer to SDRAM memory. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) +{ + uint32_t size; + __IO uint32_t *pSdramAddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *pSdramAddress = *psrcbuff; + psrcbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Reads a Words data from the SDRAM memory using DMA transfer. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to read start address + * @param pDstBuffer Pointer to destination buffer + * @param BufferSize Size of the buffer to read from memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + status = HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + if (state == HAL_SDRAM_STATE_READY) + { + hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; + } + else + { + hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt; + } + hsdram->hdma->XferErrorCallback = SDRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param pAddress Pointer to write start address + * @param pSrcBuffer Pointer to source buffer to write + * @param BufferSize Size of the buffer to write to memory + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) +{ + HAL_StatusTypeDef status; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + status = HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; + hsdram->hdma->XferErrorCallback = SDRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + status = HAL_ERROR; + } + + return status; +} + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User SDRAM Callback + * To be used to override the weak predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID + * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID + * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + state = hsdram->State; + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsdram->State == HAL_SDRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a User SDRAM Callback + * SDRAM Callback is redirected to the weak predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID + * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID + * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + state = hsdram->State; + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + break; + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsdram->State == HAL_SDRAM_STATE_RESET) + { + switch (CallbackId) + { + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User SDRAM Callback for DMA transfers + * To be used to override the weak predefined callback + * @param hsdram : SDRAM handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID + * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_SDRAM_StateTypeDef state; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsdram); + + state = hsdram->State; + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + switch (CallbackId) + { + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = pCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsdram); + return status; +} +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group3 Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically SDRAM write protection. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) +{ + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Enable write protection */ + (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Disables dynamically SDRAM write protection. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) +{ + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Disable write protection */ + (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Sends Command to the SDRAM bank. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param Command SDRAM command structure + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout) +{ + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Send SDRAM command */ + (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); + + /* Update the SDRAM controller state state */ + if (Command->CommandMode == FMC_SDRAM_CMD_PALL) + { + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + } + else + { + hsdram->State = HAL_SDRAM_STATE_READY; + } + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Programs the SDRAM Memory Refresh rate. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param RefreshRate The SDRAM refresh rate value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) +{ + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Program the refresh rate */ + (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @param AutoRefreshNumber The SDRAM auto Refresh number + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) +{ + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Set the Auto-Refresh number */ + (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Returns the SDRAM memory current mode. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval The SDRAM memory mode. + */ +uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) +{ + /* Return the SDRAM memory current mode */ + return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); +} + +/** + * @} + */ + +/** @defgroup SDRAM_Exported_Functions_Group4 State functions + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### SDRAM State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the SDRAM controller + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the SDRAM state. + * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains + * the configuration information for SDRAM module. + * @retval HAL state + */ +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram) +{ + return hsdram->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions + * @{ + */ +/** + * @brief DMA SDRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferCpltCallback(hdma); +#else + HAL_SDRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferCpltCallback(hdma); +#else + HAL_SDRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SDRAM error callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMAError(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_ERROR; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferErrorCallback(hdma); +#else + HAL_SDRAM_DMA_XferErrorCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @} + */ +/** + * @} + */ + +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* FMC_Bank5_6 */ diff --git a/libs/HALf4/src/stm32f4xx_ll_fmc.c b/libs/HALf4/src/stm32f4xx_ll_fmc.c new file mode 100644 index 00000000..94dd0c60 --- /dev/null +++ b/libs/HALf4/src/stm32f4xx_ll_fmc.c @@ -0,0 +1,1497 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_fmc.c + * @author MCD Application Team + * @brief FMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Flexible Memory Controller (FMC) peripheral memories: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### FMC peripheral features ##### + ============================================================================== + [..] The Flexible memory controller (FMC) includes following memory controllers: + (+) The NOR/PSRAM memory controller + (+) The NAND/PC Card memory controller + (+) The Synchronous DRAM (SDRAM) controller + + [..] The FMC functional block makes the interface with synchronous and asynchronous static + memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FMC performs + only one access at a time to an external device. + The main features of the FMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) 16-bit PC Card compatible devices + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + data + (+) Interface with synchronous DRAM (SDRAM) memories + (+) Independent Chip Select control for each memory bank + (+) Independent configuration for each memory bank + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ +#if defined(HAL_NOR_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\ + || defined(HAL_SRAM_MODULE_ENABLED) + +/** @defgroup FMC_LL FMC Low Layer + * @brief FMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants + * @{ + */ + +/* ----------------------- FMC registers bit mask --------------------------- */ + +#if defined(FMC_Bank1) +/* --- BCR Register ---*/ +/* BCR register clear mask */ + +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\ + FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\ + FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\ + FMC_BTR1_ACCMOD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\ + FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\ + FMC_BWTR1_ACCMOD)) +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) + +#if defined (FMC_PCR_PWAITEN) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ + FMC_PCR_PTYP | FMC_PCR_PWID | \ + FMC_PCR_ECCEN | FMC_PCR_TCLR | \ + FMC_PCR_TAR | FMC_PCR_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 |\ + FMC_PMEM_MEMHOLD2 | FMC_PMEM_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 |\ + FMC_PATT_ATTHOLD2 | FMC_PATT_ATTHIZ2)) +#else +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | \ + FMC_PCR2_PTYP | FMC_PCR2_PWID | \ + FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ + FMC_PCR2_TAR | FMC_PCR2_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 |\ + FMC_PMEM2_MEMHOLD2 | FMC_PMEM2_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 |\ + FMC_PATT2_ATTHOLD2 | FMC_PATT2_ATTHIZ2)) + +#endif /* FMC_PCR_PWAITEN */ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ +#if defined(FMC_Bank4) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR4_CLEAR_MASK ((uint32_t)(FMC_PCR4_PWAITEN | FMC_PCR4_PBKEN | \ + FMC_PCR4_PTYP | FMC_PCR4_PWID | \ + FMC_PCR4_ECCEN | FMC_PCR4_TCLR | \ + FMC_PCR4_TAR | FMC_PCR4_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM4_CLEAR_MASK ((uint32_t)(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 |\ + FMC_PMEM4_MEMHOLD4 | FMC_PMEM4_MEMHIZ4)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT4_CLEAR_MASK ((uint32_t)(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 |\ + FMC_PATT4_ATTHOLD4 | FMC_PATT4_ATTHIZ4)) + +/* --- PIO4 Register ---*/ +/* PIO4 register clear mask */ +#define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \ + FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4)) + +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) + +/* --- SDCR Register ---*/ +/* SDCR register clear mask */ +#define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \ + FMC_SDCR1_MWID | FMC_SDCR1_NB | \ + FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \ + FMC_SDCR1_RPIPE)) + +/* --- SDTR Register ---*/ +/* SDTR register clear mask */ +#define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \ + FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \ + FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)) +#endif /* FMC_Bank5_6 */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions + * @{ + */ + +#if defined(FMC_Bank1) + +/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions + * @brief NORSRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use NORSRAM device driver ##### + ============================================================================== + + [..] + This driver contains a set of APIs to interface with the FMC NORSRAM banks in order + to run the NORSRAM external devices. + + (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() + (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() + (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() + (+) FMC NORSRAM bank extended timing configuration using the function + FMC_NORSRAM_Extended_Timing_Init() + (+) FMC NORSRAM bank enable/disable write operation using the functions + FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NORSRAM interface + (+) De-initialize the FMC NORSRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the FMC_NORSRAM device according to the specified + * control parameters in the FMC_NORSRAM_InitTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Init Pointer to NORSRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + const FMC_NORSRAM_InitTypeDef *Init) +{ + uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); + assert_param(IS_FMC_MUX(Init->DataAddressMux)); + assert_param(IS_FMC_MEMORY(Init->MemoryType)); + assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); + assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); +#if defined(FMC_BCR1_WRAPMOD) + assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); +#endif /* FMC_BCR1_WRAPMOD */ + assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); + assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); + assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); + assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); + assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); + assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); +#if defined(FMC_BCR1_CCLKEN) + assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); +#endif /* FMC_BCR1_CCLKEN */ +#if defined(FMC_BCR1_WFDIS) + assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); +#endif /* FMC_BCR1_WFDIS */ + assert_param(IS_FMC_PAGESIZE(Init->PageSize)); + + /* Disable NORSRAM Device */ + __FMC_NORSRAM_DISABLE(Device, Init->NSBank); + + /* Set NORSRAM device control parameters */ + if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + else + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; + } + + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + +#if defined(FMC_BCR1_WRAPMOD) + btcr_reg |= Init->WrapMode; +#endif /* FMC_BCR1_WRAPMOD */ +#if defined(FMC_BCR1_CCLKEN) + btcr_reg |= Init->ContinuousClock; +#endif /* FMC_BCR1_CCLKEN */ +#if defined(FMC_BCR1_WFDIS) + btcr_reg |= Init->WriteFifo; +#endif /* FMC_BCR1_WFDIS */ + btcr_reg |= Init->PageSize; + + mask = (FMC_BCR1_MBKEN | + FMC_BCR1_MUXEN | + FMC_BCR1_MTYP | + FMC_BCR1_MWID | + FMC_BCR1_FACCEN | + FMC_BCR1_BURSTEN | + FMC_BCR1_WAITPOL | + FMC_BCR1_WAITCFG | + FMC_BCR1_WREN | + FMC_BCR1_WAITEN | + FMC_BCR1_EXTMOD | + FMC_BCR1_ASYNCWAIT | + FMC_BCR1_CBURSTRW); + +#if defined(FMC_BCR1_WRAPMOD) + mask |= FMC_BCR1_WRAPMOD; +#endif /* FMC_BCR1_WRAPMOD */ +#if defined(FMC_BCR1_CCLKEN) + mask |= FMC_BCR1_CCLKEN; +#endif /* FMC_BCR1_CCLKEN */ +#if defined(FMC_BCR1_WFDIS) + mask |= FMC_BCR1_WFDIS; +#endif /* FMC_BCR1_WFDIS */ + mask |= FMC_BCR1_CPSIZE; + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); + +#if defined(FMC_BCR1_CCLKEN) + /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ + if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) + { + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); + } +#endif /* FMC_BCR1_CCLKEN */ +#if defined(FMC_BCR1_WFDIS) + + if (Init->NSBank != FMC_NORSRAM_BANK1) + { + /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ + SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); + } +#endif /* FMC_BCR1_WFDIS */ + + return HAL_OK; +} + +/** + * @brief DeInitialize the FMC_NORSRAM peripheral + * @param Device Pointer to NORSRAM device instance + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable the FMC_NORSRAM device */ + __FMC_NORSRAM_DISABLE(Device, Bank); + + /* De-initialize the FMC_NORSRAM device */ + /* FMC_NORSRAM_BANK1 */ + if (Bank == FMC_NORSRAM_BANK1) + { + Device->BTCR[Bank] = 0x000030DBU; + } + /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ + else + { + Device->BTCR[Bank] = 0x000030D2U; + } + + Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; + + return HAL_OK; +} + +/** + * @brief Initialize the FMC_NORSRAM Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +{ +#if defined(FMC_BCR1_CCLKEN) + uint32_t tmpr; +#endif /* FMC_BCR1_CCLKEN */ + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set FMC_NORSRAM device timing parameters */ + Device->BTCR[Bank + 1U] = + (Timing->AddressSetupTime << FMC_BTR1_ADDSET_Pos) | + (Timing->AddressHoldTime << FMC_BTR1_ADDHLD_Pos) | + (Timing->DataSetupTime << FMC_BTR1_DATAST_Pos) | + (Timing->BusTurnAroundDuration << FMC_BTR1_BUSTURN_Pos) | + ((Timing->CLKDivision - 1U) << FMC_BTR1_CLKDIV_Pos) | + ((Timing->DataLatency - 2U) << FMC_BTR1_DATLAT_Pos) | + Timing->AccessMode; + +#if defined(FMC_BCR1_CCLKEN) + /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ + if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) + { + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos); + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); + } + +#endif /* FMC_BCR1_CCLKEN */ + return HAL_OK; +} + +/** + * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * @param ExtendedMode FMC Extended Mode + * This parameter can be one of the following values: + * @arg FMC_EXTENDED_MODE_DISABLE + * @arg FMC_EXTENDED_MODE_ENABLE + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) +{ + /* Check the parameters */ + assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) + { + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) | + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos))); + } + else + { + Device->BWTR[Bank] = 0x0FFFFFFFU; + } + + return HAL_OK; +} +/** + * @} + */ + +/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NORSRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NORSRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Enable write operation */ + SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * @param Bank NORSRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable write operation */ + CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) + +/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions + * @brief NAND Controller functions + * + @verbatim + ============================================================================== + ##### How to use NAND device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC NAND banks in order + to run the NAND external devices. + + (+) FMC NAND bank reset using the function FMC_NAND_DeInit() + (+) FMC NAND bank control configuration using the function FMC_NAND_Init() + (+) FMC NAND bank common space timing configuration using the function + FMC_NAND_CommonSpace_Timing_Init() + (+) FMC NAND bank attribute space timing configuration using the function + FMC_NAND_AttributeSpace_Timing_Init() + (+) FMC NAND bank enable/disable ECC correction feature using the functions + FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() + (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NAND interface + (+) De-initialize the FMC NAND interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_NAND device according to the specified + * control parameters in the FMC_NAND_HandleTypeDef + * @param Device Pointer to NAND device instance + * @param Init Pointer to NAND Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Init->NandBank)); + assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); + assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); + assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); + assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); + +#if defined(FMC_Bank2_3) + /* Set NAND device control parameters */ + if (Init->NandBank == FMC_NAND_BANK2) + { + /* NAND bank 2 registers configuration */ + MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos))); + } + else + { + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos))); + } +#else + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); +#endif /* FMC_Bank2_3 */ + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_NAND Common space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + +#if defined(FMC_Bank2_3) + /* Set FMC_NAND device timing parameters */ + if (Bank == FMC_NAND_BANK2) + { + /* NAND bank 2 registers configuration */ + WRITE_REG(Device->PMEM2, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos))); + } + else + { + /* NAND bank 3 registers configuration */ + WRITE_REG(Device->PMEM3, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos))); + } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + Device->PMEM = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ2_Pos)); +#endif /* FMC_Bank2_3 */ + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_NAND Attribute space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to NAND device instance + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + +#if defined(FMC_Bank2_3) + /* Set FMC_NAND device timing parameters */ + if (Bank == FMC_NAND_BANK2) + { + /* NAND bank 2 registers configuration */ + WRITE_REG(Device->PATT2, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos))); + } + else + { + /* NAND bank 3 registers configuration */ + WRITE_REG(Device->PATT3, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos))); + } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + Device->PATT = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ2_Pos)); +#endif /* FMC_Bank2_3 */ + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_NAND device + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable the NAND Bank */ + __FMC_NAND_DISABLE(Device, Bank); + + /* De-initialize the NAND Bank */ +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) + { + /* Set the FMC_NAND_BANK2 registers to their reset values */ + WRITE_REG(Device->PCR2, 0x00000018U); + WRITE_REG(Device->SR2, 0x00000040U); + WRITE_REG(Device->PMEM2, 0xFCFCFCFCU); + WRITE_REG(Device->PATT2, 0xFCFCFCFCU); + } + /* FMC_Bank3_NAND */ + else + { + /* Set the FMC_NAND_BANK3 registers to their reset values */ + WRITE_REG(Device->PCR3, 0x00000018U); + WRITE_REG(Device->SR3, 0x00000040U); + WRITE_REG(Device->PMEM3, 0xFCFCFCFCU); + WRITE_REG(Device->PATT3, 0xFCFCFCFCU); + } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* Set the FMC_NAND_BANK3 registers to their reset values */ + WRITE_REG(Device->PCR, 0x00000018U); + WRITE_REG(Device->SR, 0x00000040U); + WRITE_REG(Device->PMEM, 0xFCFCFCFCU); + WRITE_REG(Device->PATT, 0xFCFCFCFCU); +#endif /* FMC_Bank2_3 */ + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NAND Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NAND interface. + +@endverbatim + * @{ + */ + + +/** + * @brief Enables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Enable ECC feature */ +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) + { + SET_BIT(Device->PCR2, FMC_PCR2_ECCEN); + } + else + { + SET_BIT(Device->PCR3, FMC_PCR2_ECCEN); + } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + SET_BIT(Device->PCR, FMC_PCR_ECCEN); +#endif /* FMC_Bank2_3 */ + + return HAL_OK; +} + + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param Bank NAND bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable ECC feature */ +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) + { + CLEAR_BIT(Device->PCR2, FMC_PCR2_ECCEN); + } + else + { + CLEAR_BIT(Device->PCR3, FMC_PCR2_ECCEN); + } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); +#endif /* FMC_Bank2_3 */ + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * @param ECCval Pointer to ECC value + * @param Bank NAND bank number + * @param Timeout Timeout wait value + * @retval HAL status + */ +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until FIFO is empty */ + while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_TIMEOUT; + } + } + } + +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) + { + /* Get the ECCR2 register value */ + *ECCval = (uint32_t)Device->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + *ECCval = (uint32_t)Device->ECCR3; + } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* Get the ECCR register value */ + *ECCval = (uint32_t)Device->ECCR; +#endif /* FMC_Bank2_3 */ + + return HAL_OK; +} + +/** + * @} + */ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + +#if defined(FMC_Bank4) + +/** @addtogroup FMC_LL_PCCARD + * @brief PCCARD Controller functions + * + @verbatim + ============================================================================== + ##### How to use PCCARD device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC PCCARD bank in order + to run the PCCARD/compact flash external devices. + + (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit() + (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init() + (+) FMC PCCARD bank common space timing configuration using the function + FMC_PCCARD_CommonSpace_Timing_Init() + (+) FMC PCCARD bank attribute space timing configuration using the function + FMC_PCCARD_AttributeSpace_Timing_Init() + (+) FMC PCCARD bank IO space timing configuration using the function + FMC_PCCARD_IOSpace_Timing_Init() +@endverbatim + * @{ + */ + +/** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC PCCARD interface + (+) De-initialize the FMC PCCARD interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_PCCARD device according to the specified + * control parameters in the FMC_PCCARD_HandleTypeDef + * @param Device Pointer to PCCARD device instance + * @param Init Pointer to PCCARD Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, const FMC_PCCARD_InitTypeDef *Init) +{ + /* Check the parameters */ + assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) + assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); + assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + + /* Set FMC_PCCARD device control parameters */ + MODIFY_REG(Device->PCR4, + (FMC_PCR4_PTYP | + FMC_PCR4_PWAITEN | + FMC_PCR4_PWID | + FMC_PCR4_TCLR | + FMC_PCR4_TAR), + (FMC_PCR_MEMORY_TYPE_PCCARD | + Init->Waitfeature | + FMC_NAND_PCC_MEM_BUS_WIDTH_16 | + (Init->TCLRSetupTime << FMC_PCR4_TCLR_Pos) | + (Init->TARSetupTime << FMC_PCR4_TAR_Pos))); + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_PCCARD Common space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + const FMC_NAND_PCC_TimingTypeDef *Timing) +{ + /* Check the parameters */ + assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + + /* Set PCCARD timing parameters */ + WRITE_REG(Device->PMEM4, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM4_MEMHIZ4_Pos))); + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + const FMC_NAND_PCC_TimingTypeDef *Timing) +{ + /* Check the parameters */ + assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + + /* Set PCCARD timing parameters */ + WRITE_REG(Device->PATT4, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT4_ATTHIZ4_Pos))); + + return HAL_OK; +} + +/** + * @brief Initializes the FMC_PCCARD IO space Timing according to the specified + * parameters in the FMC_NAND_PCC_TimingTypeDef + * @param Device Pointer to PCCARD device instance + * @param Timing Pointer to PCCARD timing structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + const FMC_NAND_PCC_TimingTypeDef *Timing) +{ + /* Check the parameters */ + assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + + /* Set FMC_PCCARD device timing parameters */ + WRITE_REG(Device->PIO4, (Timing->SetupTime | + (Timing->WaitSetupTime << FMC_PIO4_IOWAIT4_Pos) | + (Timing->HoldSetupTime << FMC_PIO4_IOHOLD4_Pos) | + (Timing->HiZSetupTime << FMC_PIO4_IOHIZ4_Pos))); + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_PCCARD device + * @param Device Pointer to PCCARD device instance + * @retval HAL status + */ +HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) +{ + /* Check the parameters */ + assert_param(IS_FMC_PCCARD_DEVICE(Device)); + + /* Disable the FMC_PCCARD device */ + __FMC_PCCARD_DISABLE(Device); + + /* De-initialize the FMC_PCCARD device */ + Device->PCR4 = 0x00000018U; + Device->SR4 = 0x00000040U; + Device->PMEM4 = 0xFCFCFCFCU; + Device->PATT4 = 0xFCFCFCFCU; + Device->PIO4 = 0xFCFCFCFCU; + + return HAL_OK; +} + +/** + * @} + */ +#endif /* FMC_Bank4 */ + +#if defined(FMC_Bank5_6) + +/** @defgroup FMC_LL_SDRAM + * @brief SDRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use SDRAM device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC SDRAM banks in order + to run the SDRAM external devices. + + (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() + (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() + (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() + (+) FMC SDRAM bank enable/disable write operation using the functions + FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() + (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() + +@endverbatim + * @{ + */ + +/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC SDRAM interface + (+) De-initialize the FMC SDRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_SDRAM device according to the specified + * control parameters in the FMC_SDRAM_InitTypeDef + * @param Device Pointer to SDRAM device instance + * @param Init Pointer to SDRAM Initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); + assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); + assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); + assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); + assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); + assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); + assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); + + /* Set SDRAM bank configuration parameters */ + if (Init->SDBank == FMC_SDRAM_BANK1) + { + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + SDCR_CLEAR_MASK, + (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection | + Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); + } + else /* FMC_Bank2_SDRAM */ + { + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + FMC_SDCR1_SDCLK | + FMC_SDCR1_RBURST | + FMC_SDCR1_RPIPE, + (Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); + + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], + SDCR_CLEAR_MASK, + (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection)); + } + + return HAL_OK; +} + + +/** + * @brief Initializes the FMC_SDRAM device timing according to the specified + * parameters in the FMC_SDRAM_TimingTypeDef + * @param Device Pointer to SDRAM device instance + * @param Timing Pointer to SDRAM Timing structure + * @param Bank SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); + assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); + assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); + assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); + assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); + assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); + assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Set SDRAM device timing parameters */ + if (Bank == FMC_SDRAM_BANK1) + { + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + SDTR_CLEAR_MASK, + (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | + (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); + } + else /* FMC_Bank2_SDRAM */ + { + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + FMC_SDTR1_TRC | + FMC_SDTR1_TRP, + (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos)); + + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], + SDTR_CLEAR_MASK, + (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); + } + + return HAL_OK; +} + +/** + * @brief DeInitializes the FMC_SDRAM peripheral + * @param Device Pointer to SDRAM device instance + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* De-initialize the SDRAM device */ + Device->SDCR[Bank] = 0x000002D0U; + Device->SDTR[Bank] = 0x0FFFFFFFU; + Device->SDCMR = 0x00000000U; + Device->SDRTR = 0x00000000U; + Device->SDSR = 0x00000000U; + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_SDRAM write protection. + * @param Device Pointer to SDRAM device instance + * @param Bank SDRAM bank number + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Enable write protection */ + SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Disables dynamically FMC_SDRAM write protection. + * @param hsdram FMC_SDRAM handle + * @retval HAL status + */ +HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Disable write protection */ + CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); + + return HAL_OK; +} + +/** + * @brief Send Command to the FMC SDRAM bank + * @param Device Pointer to SDRAM device instance + * @param Command Pointer to SDRAM command structure + * @param Timing Pointer to SDRAM Timing structure + * @param Timeout Timeout wait value + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); + assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); + + /* Set command register */ + MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD), + ((Command->CommandMode) | (Command->CommandTarget) | + (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | + ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); + /* Get tick */ + tickstart = HAL_GetTick(); + + /* wait until command is send */ + while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Program the SDRAM Memory Refresh rate. + * @param Device Pointer to SDRAM device instance + * @param RefreshRate The SDRAM refresh rate value. + * @retval HAL state + */ +HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); + + /* Set the refresh rate in command register */ + MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); + + return HAL_OK; +} + +/** + * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. + * @param Device Pointer to SDRAM device instance + * @param AutoRefreshNumber Specifies the auto Refresh number. + * @retval None + */ +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); + + /* Set the Auto-refresh number in command register */ + MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); + + return HAL_OK; +} + +/** + * @brief Returns the indicated FMC SDRAM bank mode status. + * @param Device Pointer to SDRAM device instance + * @param Bank Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @retval The FMC SDRAM bank mode status, could be on of the following values: + * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or + * FMC_SDRAM_POWER_DOWN_MODE. + */ +uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Get the corresponding bank mode */ + if (Bank == FMC_SDRAM_BANK1) + { + tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); + } + else + { + tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); + } + + /* Return the mode status */ + return tmpreg; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FMC_Bank5_6 */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_NOR_MODULE_ENABLED */ +/** + * @} + */ +/** + * @} + */ From 53f50f20d1fb392270a87d0fe76299948fe4ae86 Mon Sep 17 00:00:00 2001 From: DannyCato Date: Sun, 29 Mar 2026 21:07:47 -0400 Subject: [PATCH 2/5] Fixed small error with sdram.h exported function (that should not be an issue but cmake) --- libs/HALf4/include/HALf4/stm32f4xx_hal_sdram.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/HALf4/include/HALf4/stm32f4xx_hal_sdram.h b/libs/HALf4/include/HALf4/stm32f4xx_hal_sdram.h index 3d450a03..856772dd 100644 --- a/libs/HALf4/include/HALf4/stm32f4xx_hal_sdram.h +++ b/libs/HALf4/include/HALf4/stm32f4xx_hal_sdram.h @@ -212,7 +212,7 @@ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); * @{ */ /* SDRAM State functions ********************************************************/ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); +HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(const SDRAM_HandleTypeDef *hsdram); /** * @} */ From 3f9b883309357a7f3e4b42541ea63738572c6ca0 Mon Sep 17 00:00:00 2001 From: DannyCato Date: Sun, 29 Mar 2026 22:10:02 -0400 Subject: [PATCH 3/5] Add const qualifier to pinky promise that we wont change the value of certain structs --- libs/HALf4/include/HALf4/stm32f4xx_ll_fmc.h | 22 ++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/libs/HALf4/include/HALf4/stm32f4xx_ll_fmc.h b/libs/HALf4/include/HALf4/stm32f4xx_ll_fmc.h index fe28f876..b6b31be8 100644 --- a/libs/HALf4/include/HALf4/stm32f4xx_ll_fmc.h +++ b/libs/HALf4/include/HALf4/stm32f4xx_ll_fmc.h @@ -1283,11 +1283,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -1315,11 +1315,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -1330,7 +1330,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -1370,9 +1370,9 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} @@ -1384,11 +1384,11 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); + const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); -uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} */ From 34aa815b370b8c1f2829053e6e029c51094b1891 Mon Sep 17 00:00:00 2001 From: DannyCato Date: Sun, 29 Mar 2026 22:10:43 -0400 Subject: [PATCH 4/5] Commented out unnecessary variable --- src/core/platform/f4xx/stm32f446xx.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/core/platform/f4xx/stm32f446xx.cpp b/src/core/platform/f4xx/stm32f446xx.cpp index 6cb566cd..8758829c 100644 --- a/src/core/platform/f4xx/stm32f446xx.cpp +++ b/src/core/platform/f4xx/stm32f446xx.cpp @@ -11,7 +11,7 @@ void stm32f4xx_init() { HAL_Init(); RCC_OscInitTypeDef RCC_OscInitStruct = {0}; RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + // RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; /** Configure the main internal regulator output voltage */ From 5ecac450594f208da4220e00ef4a754046bf9062 Mon Sep 17 00:00:00 2001 From: GitHub Build Date: Mon, 30 Mar 2026 02:12:54 +0000 Subject: [PATCH 5/5] Applied Formatting Changes During GitHub Build --- src/core/platform/f4xx/stm32f446xx.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/core/platform/f4xx/stm32f446xx.cpp b/src/core/platform/f4xx/stm32f446xx.cpp index 8758829c..6d8b1d70 100644 --- a/src/core/platform/f4xx/stm32f446xx.cpp +++ b/src/core/platform/f4xx/stm32f446xx.cpp @@ -9,8 +9,8 @@ namespace core::platform { void stm32f4xx_init() { HAL_Init(); - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; // RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; /** Configure the main internal regulator output voltage