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[CodeGenPrepare] sinkCmpExpression - don't sink larger than legal integer comparisons
A generic alternative to llvm#166564 - make the assumption that expanding integer comparisons will be expensive if the are larger than the largest legal type Thumb codegen seems to suffer more than most Fixes llvm#166534
1 parent 4830e63 commit 74a1f98

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7 files changed

+116
-149
lines changed

7 files changed

+116
-149
lines changed

‎llvm/lib/CodeGen/CodeGenPrepare.cpp‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1839,14 +1839,21 @@ bool CodeGenPrepare::unfoldPowerOf2Test(CmpInst *Cmp) {
18391839
/// lose; some adjustment may be wanted there.
18401840
///
18411841
/// Return true if any changes are made.
1842-
static bool sinkCmpExpression(CmpInst *Cmp, const TargetLowering &TLI) {
1842+
static bool sinkCmpExpression(CmpInst *Cmp, const TargetLowering &TLI,
1843+
const DataLayout &DL) {
18431844
if (TLI.hasMultipleConditionRegisters(EVT::getEVT(Cmp->getType())))
18441845
return false;
18451846

18461847
// Avoid sinking soft-FP comparisons, since this can move them into a loop.
18471848
if (TLI.useSoftFloat() && isa<FCmpInst>(Cmp))
18481849
return false;
18491850

1851+
// Avoid sinking larger than legal integer comparisons.
1852+
if (Cmp->getOperand(0)->getType()->isIntegerTy() &&
1853+
Cmp->getOperand(0)->getType()->getScalarSizeInBits() >
1854+
DL.getLargestLegalIntTypeSizeInBits())
1855+
return false;
1856+
18501857
// Only insert a cmp in each block once.
18511858
DenseMap<BasicBlock *, CmpInst *> InsertedCmps;
18521859

@@ -2224,7 +2231,7 @@ bool CodeGenPrepare::optimizeURem(Instruction *Rem) {
22242231
}
22252232

22262233
bool CodeGenPrepare::optimizeCmp(CmpInst *Cmp, ModifyDT &ModifiedDT) {
2227-
if (sinkCmpExpression(Cmp, *TLI))
2234+
if (sinkCmpExpression(Cmp, *TLI, *DL))
22282235
return true;
22292236

22302237
if (combineToUAddWithOverflow(Cmp, ModifiedDT))

‎llvm/test/CodeGen/ARM/consthoist-icmpimm.ll‎

Lines changed: 22 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -39,46 +39,50 @@ define i32 @icmp64_sge_0(i64 %x, i64 %y, i32 %a, i32 %b, i1 %c) {
3939
;
4040
; CHECKV7M-LABEL: icmp64_sge_0:
4141
; CHECKV7M: @ %bb.0:
42+
; CHECKV7M-NEXT: mvns r0, r1
43+
; CHECKV7M-NEXT: lsrs r2, r0, #31
4244
; CHECKV7M-NEXT: ldr r0, [sp, #8]
4345
; CHECKV7M-NEXT: lsls r0, r0, #31
44-
; CHECKV7M-NEXT: ldrd r2, r0, [sp]
46+
; CHECKV7M-NEXT: ldrd r1, r0, [sp]
4547
; CHECKV7M-NEXT: beq .LBB0_2
4648
; CHECKV7M-NEXT: @ %bb.1: @ %then
49+
; CHECKV7M-NEXT: cmp r2, #0
50+
; CHECKV7M-NEXT: mov r2, r0
51+
; CHECKV7M-NEXT: it ne
52+
; CHECKV7M-NEXT: movne r2, r1
4753
; CHECKV7M-NEXT: cmp.w r3, #-1
48-
; CHECKV7M-NEXT: mov r3, r0
49-
; CHECKV7M-NEXT: it gt
50-
; CHECKV7M-NEXT: movgt r3, r2
51-
; CHECKV7M-NEXT: cmp.w r1, #-1
5254
; CHECKV7M-NEXT: it gt
53-
; CHECKV7M-NEXT: movgt r0, r2
54-
; CHECKV7M-NEXT: add r0, r3
55+
; CHECKV7M-NEXT: movgt r0, r1
56+
; CHECKV7M-NEXT: add r0, r2
5557
; CHECKV7M-NEXT: bx lr
5658
; CHECKV7M-NEXT: .LBB0_2: @ %else
57-
; CHECKV7M-NEXT: cmp.w r1, #-1
58-
; CHECKV7M-NEXT: it gt
59-
; CHECKV7M-NEXT: movgt r0, r2
59+
; CHECKV7M-NEXT: cmp r2, #0
60+
; CHECKV7M-NEXT: it ne
61+
; CHECKV7M-NEXT: movne r0, r1
6062
; CHECKV7M-NEXT: bx lr
6163
;
6264
; CHECKV7A-LABEL: icmp64_sge_0:
6365
; CHECKV7A: @ %bb.0:
6466
; CHECKV7A-NEXT: ldr r2, [sp, #8]
67+
; CHECKV7A-NEXT: mvns r1, r1
6568
; CHECKV7A-NEXT: ldrd r12, r0, [sp]
69+
; CHECKV7A-NEXT: lsrs r1, r1, #31
6670
; CHECKV7A-NEXT: lsls r2, r2, #31
6771
; CHECKV7A-NEXT: beq .LBB0_2
6872
; CHECKV7A-NEXT: @ %bb.1: @ %then
73+
; CHECKV7A-NEXT: cmp r1, #0
74+
; CHECKV7A-NEXT: mov r1, r0
75+
; CHECKV7A-NEXT: it ne
76+
; CHECKV7A-NEXT: movne r1, r12
6977
; CHECKV7A-NEXT: cmp.w r3, #-1
70-
; CHECKV7A-NEXT: mov r2, r0
71-
; CHECKV7A-NEXT: it gt
72-
; CHECKV7A-NEXT: movgt r2, r12
73-
; CHECKV7A-NEXT: cmp.w r1, #-1
7478
; CHECKV7A-NEXT: it gt
7579
; CHECKV7A-NEXT: movgt r0, r12
76-
; CHECKV7A-NEXT: add r0, r2
80+
; CHECKV7A-NEXT: add r0, r1
7781
; CHECKV7A-NEXT: bx lr
7882
; CHECKV7A-NEXT: .LBB0_2: @ %else
79-
; CHECKV7A-NEXT: cmp.w r1, #-1
80-
; CHECKV7A-NEXT: it gt
81-
; CHECKV7A-NEXT: movgt r0, r12
83+
; CHECKV7A-NEXT: cmp r1, #0
84+
; CHECKV7A-NEXT: it ne
85+
; CHECKV7A-NEXT: movne r0, r12
8286
; CHECKV7A-NEXT: bx lr
8387
br i1 %c, label %then, label %else
8488
then:

‎llvm/test/CodeGen/RISCV/branch-on-zero.ll‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -41,11 +41,12 @@ define i64 @optbranch_64(i64 %Arg) {
4141
; RV32-NEXT: seqz a2, a0
4242
; RV32-NEXT: add a1, a1, a2
4343
; RV32-NEXT: or a2, a0, a1
44-
; RV32-NEXT: bnez a2, .LBB1_2
45-
; RV32-NEXT: # %bb.1: # %bb2
44+
; RV32-NEXT: beqz a2, .LBB1_2
45+
; RV32-NEXT: # %bb.1: # %bb3
46+
; RV32-NEXT: ret
47+
; RV32-NEXT: .LBB1_2: # %bb2
4648
; RV32-NEXT: li a0, -1
4749
; RV32-NEXT: li a1, -1
48-
; RV32-NEXT: .LBB1_2: # %bb3
4950
; RV32-NEXT: ret
5051
;
5152
; RV64-LABEL: optbranch_64:

‎llvm/test/CodeGen/RISCV/overflow-intrinsics.ll‎

Lines changed: 39 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -232,22 +232,22 @@ define i64 @uaddo3_math_overflow_used(i64 %a, i64 %b, ptr %res) nounwind ssp {
232232
ret i64 %Q
233233
}
234234

235-
; TODO? CGP sinks the compare before we have a chance to form the overflow intrinsic.
235+
; Ensure CGP doesn't sink the compare before we have a chance to form the overflow intrinsic.
236236

237237
define i64 @uaddo4(i64 %a, i64 %b, i1 %c) nounwind ssp {
238238
; RV32-LABEL: uaddo4:
239239
; RV32: # %bb.0: # %entry
240-
; RV32-NEXT: andi a4, a4, 1
241-
; RV32-NEXT: beqz a4, .LBB6_6
242-
; RV32-NEXT: # %bb.1: # %next
243240
; RV32-NEXT: add a1, a3, a1
244241
; RV32-NEXT: add a0, a2, a0
245242
; RV32-NEXT: sltu a0, a0, a2
246243
; RV32-NEXT: add a1, a1, a0
247-
; RV32-NEXT: beq a3, a1, .LBB6_3
248-
; RV32-NEXT: # %bb.2: # %next
244+
; RV32-NEXT: andi a4, a4, 1
245+
; RV32-NEXT: beq a3, a1, .LBB6_2
246+
; RV32-NEXT: # %bb.1: # %entry
249247
; RV32-NEXT: sltu a0, a1, a3
250-
; RV32-NEXT: .LBB6_3: # %next
248+
; RV32-NEXT: .LBB6_2: # %entry
249+
; RV32-NEXT: beqz a4, .LBB6_6
250+
; RV32-NEXT: # %bb.3: # %next
251251
; RV32-NEXT: bnez a0, .LBB6_5
252252
; RV32-NEXT: # %bb.4: # %next
253253
; RV32-NEXT: li a2, 42
@@ -292,19 +292,19 @@ exit:
292292
define i64 @uaddo5(i64 %a, i64 %b, ptr %ptr, i1 %c) nounwind ssp {
293293
; RV32-LABEL: uaddo5:
294294
; RV32: # %bb.0: # %entry
295+
; RV32-NEXT: add a6, a3, a1
296+
; RV32-NEXT: add a1, a2, a0
297+
; RV32-NEXT: sltu a0, a1, a2
298+
; RV32-NEXT: add a6, a6, a0
295299
; RV32-NEXT: andi a5, a5, 1
296-
; RV32-NEXT: add a1, a3, a1
297-
; RV32-NEXT: add a6, a2, a0
298-
; RV32-NEXT: sltu a0, a6, a2
299-
; RV32-NEXT: add a1, a1, a0
300-
; RV32-NEXT: sw a6, 0(a4)
301-
; RV32-NEXT: sw a1, 4(a4)
300+
; RV32-NEXT: beq a6, a3, .LBB7_2
301+
; RV32-NEXT: # %bb.1: # %entry
302+
; RV32-NEXT: sltu a0, a6, a3
303+
; RV32-NEXT: .LBB7_2: # %entry
304+
; RV32-NEXT: sw a1, 0(a4)
305+
; RV32-NEXT: sw a6, 4(a4)
302306
; RV32-NEXT: beqz a5, .LBB7_6
303-
; RV32-NEXT: # %bb.1: # %next
304-
; RV32-NEXT: beq a3, a1, .LBB7_3
305-
; RV32-NEXT: # %bb.2: # %next
306-
; RV32-NEXT: sltu a0, a1, a3
307-
; RV32-NEXT: .LBB7_3: # %next
307+
; RV32-NEXT: # %bb.3: # %next
308308
; RV32-NEXT: bnez a0, .LBB7_5
309309
; RV32-NEXT: # %bb.4: # %next
310310
; RV32-NEXT: li a2, 42
@@ -1076,41 +1076,37 @@ define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, ptr %p, i1 %cond) {
10761076
; RV32-NEXT: .cfi_offset s4, -24
10771077
; RV32-NEXT: .cfi_offset s5, -28
10781078
; RV32-NEXT: .cfi_offset s6, -32
1079-
; RV32-NEXT: mv s5, a5
1080-
; RV32-NEXT: mv s3, a1
1079+
; RV32-NEXT: mv s1, a5
1080+
; RV32-NEXT: mv s4, a1
10811081
; RV32-NEXT: andi a1, a5, 1
1082-
; RV32-NEXT: beqz a1, .LBB32_8
1082+
; RV32-NEXT: beqz a1, .LBB32_6
10831083
; RV32-NEXT: # %bb.1: # %t
10841084
; RV32-NEXT: mv s0, a4
1085-
; RV32-NEXT: mv s2, a3
1086-
; RV32-NEXT: mv s1, a2
1087-
; RV32-NEXT: mv s4, a0
1088-
; RV32-NEXT: beq s3, a3, .LBB32_3
1085+
; RV32-NEXT: mv s3, a3
1086+
; RV32-NEXT: mv s2, a2
1087+
; RV32-NEXT: mv s5, a0
1088+
; RV32-NEXT: beq s4, a3, .LBB32_3
10891089
; RV32-NEXT: # %bb.2: # %t
1090-
; RV32-NEXT: sltu s6, s3, s2
1090+
; RV32-NEXT: sltu s6, s4, s3
10911091
; RV32-NEXT: j .LBB32_4
10921092
; RV32-NEXT: .LBB32_3:
1093-
; RV32-NEXT: sltu s6, s4, s1
1093+
; RV32-NEXT: sltu s6, s5, s2
10941094
; RV32-NEXT: .LBB32_4: # %t
10951095
; RV32-NEXT: mv a0, s6
10961096
; RV32-NEXT: call call
1097-
; RV32-NEXT: beqz s6, .LBB32_8
1097+
; RV32-NEXT: beqz s6, .LBB32_6
10981098
; RV32-NEXT: # %bb.5: # %end
1099-
; RV32-NEXT: sltu a1, s4, s1
1100-
; RV32-NEXT: mv a0, a1
1101-
; RV32-NEXT: beq s3, s2, .LBB32_7
1102-
; RV32-NEXT: # %bb.6: # %end
1103-
; RV32-NEXT: sltu a0, s3, s2
1104-
; RV32-NEXT: .LBB32_7: # %end
1105-
; RV32-NEXT: sub a2, s3, s2
1106-
; RV32-NEXT: sub a3, s4, s1
1107-
; RV32-NEXT: sub a2, a2, a1
1108-
; RV32-NEXT: sw a3, 0(s0)
1109-
; RV32-NEXT: sw a2, 4(s0)
1110-
; RV32-NEXT: j .LBB32_9
1111-
; RV32-NEXT: .LBB32_8: # %f
1112-
; RV32-NEXT: mv a0, s5
1113-
; RV32-NEXT: .LBB32_9: # %f
1099+
; RV32-NEXT: sltu a0, s5, s2
1100+
; RV32-NEXT: sub a1, s4, s3
1101+
; RV32-NEXT: sub a2, s5, s2
1102+
; RV32-NEXT: sub a1, a1, a0
1103+
; RV32-NEXT: sw a2, 0(s0)
1104+
; RV32-NEXT: sw a1, 4(s0)
1105+
; RV32-NEXT: mv a0, s6
1106+
; RV32-NEXT: j .LBB32_7
1107+
; RV32-NEXT: .LBB32_6: # %f
1108+
; RV32-NEXT: mv a0, s1
1109+
; RV32-NEXT: .LBB32_7: # %f
11141110
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
11151111
; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
11161112
; RV32-NEXT: lw s1, 20(sp) # 4-byte Folded Reload

‎llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,14 +59,14 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
5959
; RV32-NEXT: sltu t5, a0, t6
6060
; RV32-NEXT: sltu t6, a2, t3
6161
; RV32-NEXT: and t5, t5, t6
62+
; RV32-NEXT: sltu t1, a6, t1
6263
; RV32-NEXT: sltu t4, a0, t4
6364
; RV32-NEXT: sltu t3, a4, t3
6465
; RV32-NEXT: and t3, t4, t3
6566
; RV32-NEXT: or t4, a1, a3
6667
; RV32-NEXT: srli t4, t4, 31
6768
; RV32-NEXT: or t4, t5, t4
6869
; RV32-NEXT: or t5, a1, a5
69-
; RV32-NEXT: sltu t1, a6, t1
7070
; RV32-NEXT: srli t5, t5, 31
7171
; RV32-NEXT: or t3, t3, t5
7272
; RV32-NEXT: or t3, t4, t3

‎llvm/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll‎

Lines changed: 25 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -34,16 +34,16 @@ define void @f(ptr nocapture %arg, ptr nocapture %arg1, ptr nocapture %arg2, ptr
3434
; CHECK-NEXT: .cfi_offset %edi, -16
3535
; CHECK-NEXT: .cfi_offset %ebx, -12
3636
; CHECK-NEXT: xorl %eax, %eax
37-
; CHECK-NEXT: xorl %edi, %edi
37+
; CHECK-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill
3838
; CHECK-NEXT: testb %al, %al
39-
; CHECK-NEXT: Ltmp0:
40-
; CHECK-NEXT: ## implicit-def: $ebx
39+
; CHECK-NEXT: Ltmp0: ## EH_LABEL
40+
; CHECK-NEXT: ## implicit-def: $edi
4141
; CHECK-NEXT: calll __Znam
42-
; CHECK-NEXT: Ltmp1:
42+
; CHECK-NEXT: Ltmp1: ## EH_LABEL
4343
; CHECK-NEXT: ## %bb.1: ## %bb11
4444
; CHECK-NEXT: movl %eax, %esi
45-
; CHECK-NEXT: movb $1, %al
46-
; CHECK-NEXT: testb %al, %al
45+
; CHECK-NEXT: movb $1, %bl
46+
; CHECK-NEXT: testb %bl, %bl
4747
; CHECK-NEXT: jne LBB0_2
4848
; CHECK-NEXT: ## %bb.7: ## %bb31
4949
; CHECK-NEXT: ## implicit-def: $eax
@@ -53,23 +53,20 @@ define void @f(ptr nocapture %arg, ptr nocapture %arg1, ptr nocapture %arg2, ptr
5353
; CHECK-NEXT: ## Child Loop BB0_13 Depth 2
5454
; CHECK-NEXT: ## Child Loop BB0_16 Depth 3
5555
; CHECK-NEXT: ## Child Loop BB0_21 Depth 2
56-
; CHECK-NEXT: movb $1, %al
57-
; CHECK-NEXT: testb %al, %al
56+
; CHECK-NEXT: testb %bl, %bl
5857
; CHECK-NEXT: jne LBB0_9
5958
; CHECK-NEXT: ## %bb.10: ## %bb41
6059
; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1
61-
; CHECK-NEXT: Ltmp2:
60+
; CHECK-NEXT: Ltmp2: ## EH_LABEL
6261
; CHECK-NEXT: xorl %eax, %eax
6362
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
6463
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
6564
; CHECK-NEXT: movl %esi, (%esp)
6665
; CHECK-NEXT: calll _Pjii
67-
; CHECK-NEXT: Ltmp3:
66+
; CHECK-NEXT: Ltmp3: ## EH_LABEL
6867
; CHECK-NEXT: ## %bb.11: ## %bb42
6968
; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1
70-
; CHECK-NEXT: xorl %eax, %eax
71-
; CHECK-NEXT: decl %eax
72-
; CHECK-NEXT: testl %eax, %eax
69+
; CHECK-NEXT: testb %bl, %bl
7370
; CHECK-NEXT: jne LBB0_18
7471
; CHECK-NEXT: ## %bb.12: ## %bb45.preheader
7572
; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1
@@ -78,8 +75,7 @@ define void @f(ptr nocapture %arg, ptr nocapture %arg1, ptr nocapture %arg2, ptr
7875
; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1
7976
; CHECK-NEXT: ## => This Loop Header: Depth=2
8077
; CHECK-NEXT: ## Child Loop BB0_16 Depth 3
81-
; CHECK-NEXT: movb $1, %cl
82-
; CHECK-NEXT: testb %cl, %cl
78+
; CHECK-NEXT: testb %bl, %bl
8379
; CHECK-NEXT: jne LBB0_19
8480
; CHECK-NEXT: ## %bb.14: ## %bb48
8581
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=2
@@ -88,14 +84,14 @@ define void @f(ptr nocapture %arg, ptr nocapture %arg1, ptr nocapture %arg2, ptr
8884
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=2
8985
; CHECK-NEXT: xorl %ecx, %ecx
9086
; CHECK-NEXT: movl %esi, %edx
91-
; CHECK-NEXT: movl %edi, %ebx
87+
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi ## 4-byte Reload
9288
; CHECK-NEXT: LBB0_16: ## %bb49
9389
; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1
9490
; CHECK-NEXT: ## Parent Loop BB0_13 Depth=2
9591
; CHECK-NEXT: ## => This Inner Loop Header: Depth=3
9692
; CHECK-NEXT: incl %ecx
9793
; CHECK-NEXT: addl $4, %edx
98-
; CHECK-NEXT: decl %ebx
94+
; CHECK-NEXT: decl %edi
9995
; CHECK-NEXT: jne LBB0_16
10096
; CHECK-NEXT: LBB0_17: ## %bb57
10197
; CHECK-NEXT: ## in Loop: Header=BB0_13 Depth=2
@@ -107,13 +103,12 @@ define void @f(ptr nocapture %arg, ptr nocapture %arg1, ptr nocapture %arg2, ptr
107103
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
108104
; CHECK-NEXT: movl $0, (%esp)
109105
; CHECK-NEXT: calll ___bzero
110-
; CHECK-NEXT: movb $1, %al
111-
; CHECK-NEXT: testb %al, %al
106+
; CHECK-NEXT: testb %bl, %bl
112107
; CHECK-NEXT: jne LBB0_22
113108
; CHECK-NEXT: ## %bb.20: ## %bb61.preheader
114109
; CHECK-NEXT: ## in Loop: Header=BB0_8 Depth=1
115110
; CHECK-NEXT: movl %esi, %eax
116-
; CHECK-NEXT: movl %edi, %ecx
111+
; CHECK-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx ## 4-byte Reload
117112
; CHECK-NEXT: LBB0_21: ## %bb61
118113
; CHECK-NEXT: ## Parent Loop BB0_8 Depth=1
119114
; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
@@ -126,32 +121,32 @@ define void @f(ptr nocapture %arg, ptr nocapture %arg1, ptr nocapture %arg2, ptr
126121
; CHECK-NEXT: decl {{[-0-9]+}}(%e{{[sb]}}p) ## 4-byte Folded Spill
127122
; CHECK-NEXT: jmp LBB0_8
128123
; CHECK-NEXT: LBB0_18: ## %bb43
129-
; CHECK-NEXT: Ltmp5:
130-
; CHECK-NEXT: movl %esi, %ebx
124+
; CHECK-NEXT: Ltmp5: ## EH_LABEL
125+
; CHECK-NEXT: movl %esi, %edi
131126
; CHECK-NEXT: calll _OnOverFlow
132-
; CHECK-NEXT: Ltmp6:
127+
; CHECK-NEXT: Ltmp6: ## EH_LABEL
133128
; CHECK-NEXT: jmp LBB0_3
134129
; CHECK-NEXT: LBB0_2: ## %bb29
135-
; CHECK-NEXT: Ltmp7:
136-
; CHECK-NEXT: movl %esi, %ebx
130+
; CHECK-NEXT: Ltmp7: ## EH_LABEL
131+
; CHECK-NEXT: movl %esi, %edi
137132
; CHECK-NEXT: calll _OnOverFlow
138-
; CHECK-NEXT: Ltmp8:
133+
; CHECK-NEXT: Ltmp8: ## EH_LABEL
139134
; CHECK-NEXT: LBB0_3: ## %bb30
140135
; CHECK-NEXT: ud2
141136
; CHECK-NEXT: LBB0_4: ## %bb20.loopexit
142-
; CHECK-NEXT: Ltmp4:
137+
; CHECK-NEXT: Ltmp4: ## EH_LABEL
143138
; CHECK-NEXT: LBB0_9:
144-
; CHECK-NEXT: movl %esi, %ebx
139+
; CHECK-NEXT: movl %esi, %edi
145140
; CHECK-NEXT: LBB0_6: ## %bb23
146-
; CHECK-NEXT: testl %ebx, %ebx
141+
; CHECK-NEXT: testl %edi, %edi
147142
; CHECK-NEXT: addl $28, %esp
148143
; CHECK-NEXT: popl %esi
149144
; CHECK-NEXT: popl %edi
150145
; CHECK-NEXT: popl %ebx
151146
; CHECK-NEXT: popl %ebp
152147
; CHECK-NEXT: retl
153148
; CHECK-NEXT: LBB0_5: ## %bb20.loopexit.split-lp
154-
; CHECK-NEXT: Ltmp9:
149+
; CHECK-NEXT: Ltmp9: ## EH_LABEL
155150
; CHECK-NEXT: jmp LBB0_6
156151
; CHECK-NEXT: Lfunc_end0:
157152
bb:

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