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bing-mabing-ma
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[gfx12] Add support for gfx1200 (#131)
* [gfx12] Add support for gfx1200 * [gfx12] Rename CP_PERFMON_CNTL_1 to CP_PERFMON_CNTL for better compatibility
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+62
-22
lines changed

5 files changed

+62
-22
lines changed

‎gfxip/gfx12/gfx12_block_info.h‎

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -97,28 +97,28 @@ enum SpmSeBlockId {
9797
SPM_SE_BLOCK_NAME_LAST = SPM_SE_BLOCK_NAME_UTCL1,
9898
};
9999

100-
namespace gfx1201 {
101-
// IP versions for Radeon RX 9070
102-
// ip_block : gc_12_0_1
100+
namespace gfx1200 {
103101
// ip_block : athub_4_1_0
102+
// ip_block : gc_12_0_0
103+
// ip_block : sdma_7_0_0
104104

105105
// Number of block instances
106106
// Reference: global_features.h (from gfxip header file package)
107107
static const uint32_t ChaCounterBlockNumInstances = 1;
108-
static const uint32_t ChcCounterBlockNumInstances = 4;
108+
static const uint32_t ChcCounterBlockNumInstances = 2;
109109
static const uint32_t CpcCounterBlockNumInstances = 1;
110110
static const uint32_t CpfCounterBlockNumInstances = 1;
111111
static const uint32_t CpgCounterBlockNumInstances = 1;
112112
static const uint32_t GcmcVmL2CounterBlockNumInstances = 1;
113113
static const uint32_t GcrCounterBlockNumInstances = 1;
114114
static const uint32_t Gcutcl2CounterBlockNumInstances = 1;
115115
static const uint32_t Gcvml2CounterBlockNumInstances = 1;
116-
static const uint32_t GcEaCpwdCounterBlockNumInstances = 36;
117-
static const uint32_t GcEaSeCounterBlockNumInstances = 4;
116+
static const uint32_t GcEaCpwdCounterBlockNumInstances = 18;
117+
static const uint32_t GcEaSeCounterBlockNumInstances = 8;
118118
static const uint32_t Gl1aCounterBlockNumInstances = 1;
119119
static const uint32_t Gl1cCounterBlockNumInstances = 4;
120120
static const uint32_t Gl2aCounterBlockNumInstances = 4;
121-
static const uint32_t Gl2cCounterBlockNumInstances = 32;
121+
static const uint32_t Gl2cCounterBlockNumInstances = 16;
122122
static const uint32_t GrbmCounterBlockNumInstances = 1;
123123
static const uint32_t GrbmhCounterBlockNumInstances = 1;
124124
static const uint32_t RlcCounterBlockNumInstances = 1;
@@ -190,6 +190,18 @@ static const uint32_t TaCounterBlockMaxEvent = 254;
190190
static const uint32_t TcpCounterBlockMaxEvent = 99;
191191
static const uint32_t TdCounterBlockMaxEvent = 271;
192192
static const uint32_t Utcl1CounterBlockMaxEvent = 71;
193+
} // namespace gfx1200
194+
195+
namespace gfx1201 {
196+
// ip_block : athub_4_1_0
197+
// ip_block : gc_12_0_1
198+
// ip_block : sdma_7_0_1
199+
200+
// Number of block instances
201+
static const uint32_t ChcCounterBlockNumInstances = 4;
202+
static const uint32_t GcEaCpwdCounterBlockNumInstances = 36;
203+
static const uint32_t GcEaSeCounterBlockNumInstances = 4;
204+
static const uint32_t Gl2cCounterBlockNumInstances = 32;
193205
} // namespace gfx1201
194206

195207
static const uint32_t SdmaCounterBlockMaxInstances = 8;

‎gfxip/gfx12/gfx12_block_table.h‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@
5656

5757
namespace gfxip {
5858
namespace gfx12 {
59-
namespace gfx1201 {
59+
namespace gfx1200 {
6060
// Counter register info - Auto-generated from chip_offset_byte.h, edit with extra caution
6161
static const CounterRegInfo ChaCounterRegAddr[] = {REG_INFO_4(CHA)};
6262
static const CounterRegInfo ChcCounterRegAddr[] = {REG_INFO_4(CHC)};
@@ -142,7 +142,15 @@ static const GpuBlockInfo SqcCounterBlockInfo = {"SQ", __BLOCK_ID_HSA(SQ), SqcCo
142142
static const GpuBlockInfo TaCounterBlockInfo = {"TA", __BLOCK_ID_HSA(TA), TaCounterBlockNumInstances, TaCounterBlockMaxEvent, TaCounterBlockNumCounters, TaCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockTcAttr, NULL/*TaBlockDelayInfo*/, SPM_SE_BLOCK_NAME_TA};
143143
static const GpuBlockInfo TdCounterBlockInfo = {"TD", __BLOCK_ID_HSA(TD), TdCounterBlockNumInstances, TdCounterBlockMaxEvent, TdCounterBlockNumCounters, TdCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockTcAttr, NULL/*TdBlockDelayInfo*/, SPM_SE_BLOCK_NAME_TD};
144144
static const GpuBlockInfo TcpCounterBlockInfo = {"TCP", __BLOCK_ID_HSA(TCP), TcpCounterBlockNumInstances, TcpCounterBlockMaxEvent, TcpCounterBlockNumCounters, TcpCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr|CounterBlockSaAttr|CounterBlockWgpAttr|CounterBlockTcAttr, NULL/*TdBlockDelayInfo*/, SPM_SE_BLOCK_NAME_TCP};
145-
} // namespace gfx12xx
145+
} // namespace gfx1200
146+
147+
namespace gfx1201 {
148+
static const GpuBlockInfo Gl2cCounterBlockInfo = {"GL2C", __BLOCK_ID_HSA(GL2C), gfx1201::Gl2cCounterBlockNumInstances, Gl2cCounterBlockMaxEvent, Gl2cCounterBlockNumCounters, Gl2cCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr};
149+
static const GpuBlockInfo ChcCounterBlockInfo = {"CHC", __BLOCK_ID(CHC), gfx1201::ChcCounterBlockNumInstances, ChcCounterBlockMaxEvent, ChcCounterBlockNumCounters, ChcCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr|CounterBlockTcAttr};
150+
static const GpuBlockInfo GceaCounterBlockInfo = {"GCEA", __BLOCK_ID_HSA(GCEA), gfx1201::GcEaCpwdCounterBlockNumInstances, GcEaCpwdCounterBlockMaxEvent, GcEaCpwdCounterBlockNumCounters, GcEaCpwdCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockDfltAttr};
151+
static const GpuBlockInfo GceaSeCounterBlockInfo = {"GCEA_SE", __BLOCK_ID(GCEA_SE), gfx1201::GcEaSeCounterBlockNumInstances, GcEaSeCounterBlockMaxEvent, GcEaSeCounterBlockNumCounters, GcEaSeCounterRegAddr, gfx12_cntx_prim::select_value, CounterBlockSeAttr};
152+
} // namespace gfx1201
153+
146154
} // namespace gfx12
147155
} // namespace gfxip
148156

‎gfxip/gfx12/gfx12_primitives.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ class gfx12_cntx_prim {
4444
REG_32B_ADDR(GC, 0, regCOMPUTE_PERFCOUNT_ENABLE);
4545
static constexpr Register RLC_PERFMON_CLK_CNTL_ADDR =
4646
REG_32B_ADDR(GC, 0, regRLC_PERFMON_CNTL); // REG_32B_ADDR(GC, 0, regRLC_PERFMON_CLK_CNTL);
47-
static constexpr Register CP_PERFMON_CNTL_ADDR = REG_32B_ADDR(GC, 0, regCP_PERFMON_CNTL_1);
47+
static constexpr Register CP_PERFMON_CNTL_ADDR = REG_32B_ADDR(GC, 0, regCP_PERFMON_CNTL);
4848

4949
static constexpr Register COMPUTE_THREAD_TRACE_ENABLE_ADDR =
5050
REG_32B_ADDR(GC, 0, regCOMPUTE_THREAD_TRACE_ENABLE);
@@ -241,29 +241,29 @@ class gfx12_cntx_prim {
241241
return grbm_gfx_index;
242242
}
243243

244-
// CP_PERFMON_CNTL_1 value to reset counters
244+
// CP_PERFMON_CNTL value to reset counters
245245
static uint32_t cp_perfmon_cntl_reset_value() {
246246
uint32_t cp_perfmon_cntl{0};
247247
return cp_perfmon_cntl;
248248
}
249249

250-
// CP_PERFMON_CNTL_1 value to start counters
250+
// CP_PERFMON_CNTL value to start counters
251251
static uint32_t cp_perfmon_cntl_start_value() {
252-
uint32_t cp_perfmon_cntl = SET_REG_FIELD_BITS(CP_PERFMON_CNTL_1, PERFMON_STATE, 1);
252+
uint32_t cp_perfmon_cntl = SET_REG_FIELD_BITS(CP_PERFMON_CNTL, PERFMON_STATE, 1);
253253
return cp_perfmon_cntl;
254254
}
255255

256-
// CP_PERFMON_CNTL_1 value to stop/freeze counters
256+
// CP_PERFMON_CNTL value to stop/freeze counters
257257
static uint32_t cp_perfmon_cntl_stop_value() {
258-
uint32_t cp_perfmon_cntl = SET_REG_FIELD_BITS(CP_PERFMON_CNTL_1, PERFMON_STATE, 2) |
259-
SET_REG_FIELD_BITS(CP_PERFMON_CNTL_1, PERFMON_SAMPLE_ENABLE, 1);
258+
uint32_t cp_perfmon_cntl = SET_REG_FIELD_BITS(CP_PERFMON_CNTL, PERFMON_STATE, 2) |
259+
SET_REG_FIELD_BITS(CP_PERFMON_CNTL, PERFMON_SAMPLE_ENABLE, 1);
260260
return cp_perfmon_cntl;
261261
}
262262

263-
// CP_PERFMON_CNTL_1 value to stop/freeze counters
263+
// CP_PERFMON_CNTL value to stop/freeze counters
264264
static uint32_t cp_perfmon_cntl_read_value() {
265-
uint32_t cp_perfmon_cntl = SET_REG_FIELD_BITS(CP_PERFMON_CNTL_1, PERFMON_STATE, 1) |
266-
SET_REG_FIELD_BITS(CP_PERFMON_CNTL_1, PERFMON_SAMPLE_ENABLE, 1);
265+
uint32_t cp_perfmon_cntl = SET_REG_FIELD_BITS(CP_PERFMON_CNTL, PERFMON_STATE, 1) |
266+
SET_REG_FIELD_BITS(CP_PERFMON_CNTL, PERFMON_SAMPLE_ENABLE, 1);
267267
return cp_perfmon_cntl;
268268
}
269269

@@ -421,12 +421,12 @@ class gfx12_cntx_prim {
421421
}
422422
static uint32_t cp_perfmon_cntl_spm_start_value() {
423423
uint32_t cp_perfmon_cntl{0};
424-
cp_perfmon_cntl = SET_REG_FIELD_BITS(CP_PERFMON_CNTL_1, SPM_PERFMON_STATE, 1);
424+
cp_perfmon_cntl = SET_REG_FIELD_BITS(CP_PERFMON_CNTL, SPM_PERFMON_STATE, 1);
425425
return cp_perfmon_cntl;
426426
}
427427
static uint32_t cp_perfmon_cntl_spm_stop_value() {
428428
uint32_t cp_perfmon_cntl{0};
429-
cp_perfmon_cntl = SET_REG_FIELD_BITS(CP_PERFMON_CNTL_1, SPM_PERFMON_STATE, 2);
429+
cp_perfmon_cntl = SET_REG_FIELD_BITS(CP_PERFMON_CNTL, SPM_PERFMON_STATE, 2);
430430
return cp_perfmon_cntl;
431431
}
432432
static uint32_t rlc_spm_muxsel_data(const uint32_t& value, const counter_des_t& counter_des,

‎src/core/gfx12_factory.cpp‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,7 @@ void Gfx12Factory::ConstructBuilders(const AgentInfo* agent_info) {
7878
}
7979

8080
void Gfx12Factory::ConstructTable(const AgentInfo* agent_info) {
81+
auto agent_name = std::string_view(agent_info->name).substr(0, 7);
8182
// Global blocks
8283
block_table_[__BLOCK_ID(CHA)] = &ChaCounterBlockInfo;
8384
block_table_[__BLOCK_ID(CHC)] = &ChcCounterBlockInfo;
@@ -108,6 +109,13 @@ void Gfx12Factory::ConstructTable(const AgentInfo* agent_info) {
108109
block_table_[__BLOCK_ID_HSA(TA)] = &TaCounterBlockInfo;
109110
block_table_[__BLOCK_ID_HSA(TCP)] = &TcpCounterBlockInfo;
110111
block_table_[__BLOCK_ID_HSA(TD)] = &TdCounterBlockInfo;
112+
113+
if (agent_name == "gfx1201") {
114+
block_table_[__BLOCK_ID(CHC)] = &gfx1201::ChcCounterBlockInfo;
115+
block_table_[__BLOCK_ID_HSA(GCEA)] = &gfx1201::GceaCounterBlockInfo;
116+
block_table_[__BLOCK_ID(GCEA_SE)] = &gfx1201::GceaSeCounterBlockInfo;
117+
block_table_[__BLOCK_ID_HSA(GL2C)] = &gfx1201::Gl2cCounterBlockInfo;
118+
}
111119
}
112120

113121
// Pm4Factory create mathods

‎src/def/gfx12_def.h‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,10 +28,22 @@
2828
#include "util/reg_offsets.h"
2929
#include "linux/registers/gc/gc_12_0_0_offset.h"
3030
#include "linux/registers/gc/gc_12_0_0_sh_mask.h"
31+
// Rename CP_PERFMON_CNTL_1 to CP_PERFMON_CNTL for better compatibility
32+
// CP_PERFMON_CNTL_1
33+
#define regCP_PERFMON_CNTL_BASE_IDX regCP_PERFMON_CNTL_1_BASE_IDX
34+
#define regCP_PERFMON_CNTL regCP_PERFMON_CNTL_1
35+
#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT CP_PERFMON_CNTL_1__PERFMON_STATE__SHIFT
36+
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT CP_PERFMON_CNTL_1__SPM_PERFMON_STATE__SHIFT
37+
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT CP_PERFMON_CNTL_1__PERFMON_ENABLE_MODE__SHIFT
38+
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT CP_PERFMON_CNTL_1__PERFMON_SAMPLE_ENABLE__SHIFT
39+
#define CP_PERFMON_CNTL__PERFMON_STATE_MASK CP_PERFMON_CNTL_1__PERFMON_STATE_MASK
40+
#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK CP_PERFMON_CNTL_1__SPM_PERFMON_STATE_MASK
41+
#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK CP_PERFMON_CNTL_1__PERFMON_ENABLE_MODE_MASK
42+
#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK CP_PERFMON_CNTL_1__PERFMON_SAMPLE_ENABLE_MASK
3143
#include "linux/packets/nvd.h"
3244
#include "gfxip/gfx12/gfx12_block_info.h"
3345
using namespace gfxip::gfx12;
34-
using namespace gfxip::gfx12::gfx1201;
46+
using namespace gfxip::gfx12::gfx1200;
3547
#include "gfxip/gfx12/gfx12_primitives.h"
3648
#include "gfxip/gfx12/gfx12_block_table.h"
3749

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