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merge main into amd-staging
2 parents 0a2bac0 + bf1d4a0 commit 00b43c0

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-100
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8 files changed

+295
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‎llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include "llvm/CodeGen/GlobalISel/GISelValueTracking.h"
1515
#include "llvm/ADT/StringExtras.h"
1616
#include "llvm/Analysis/ValueTracking.h"
17+
#include "llvm/Analysis/VectorUtils.h"
1718
#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
1819
#include "llvm/CodeGen/GlobalISel/Utils.h"
1920
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -629,6 +630,33 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
629630
Known.Zero.setBitsFrom(LowBits);
630631
break;
631632
}
633+
case TargetOpcode::G_SHUFFLE_VECTOR: {
634+
APInt DemandedLHS, DemandedRHS;
635+
// Collect the known bits that are shared by every vector element referenced
636+
// by the shuffle.
637+
unsigned NumElts = MRI.getType(MI.getOperand(1).getReg()).getNumElements();
638+
if (!getShuffleDemandedElts(NumElts, MI.getOperand(3).getShuffleMask(),
639+
DemandedElts, DemandedLHS, DemandedRHS))
640+
break;
641+
642+
// Known bits are the values that are shared by every demanded element.
643+
Known.Zero.setAllBits();
644+
Known.One.setAllBits();
645+
if (!!DemandedLHS) {
646+
computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedLHS,
647+
Depth + 1);
648+
Known = Known.intersectWith(Known2);
649+
}
650+
// If we don't know any bits, early out.
651+
if (Known.isUnknown())
652+
break;
653+
if (!!DemandedRHS) {
654+
computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedRHS,
655+
Depth + 1);
656+
Known = Known.intersectWith(Known2);
657+
}
658+
break;
659+
}
632660
}
633661

634662
LLVM_DEBUG(dumpResult(MI, Known, Depth));

‎llvm/lib/Transforms/Scalar/LICM.cpp‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2877,6 +2877,13 @@ static bool hoistBOAssociation(Instruction &I, Loop &L,
28772877
if (auto *I = dyn_cast<Instruction>(Inv))
28782878
I->setFastMathFlags(Intersect);
28792879
NewBO->setFastMathFlags(Intersect);
2880+
} else if (Opcode == Instruction::Or) {
2881+
bool Disjoint = cast<PossiblyDisjointInst>(BO)->isDisjoint() &&
2882+
cast<PossiblyDisjointInst>(BO0)->isDisjoint();
2883+
// If `Inv` was not constant-folded, a new Instruction has been created.
2884+
if (auto *I = dyn_cast<PossiblyDisjointInst>(Inv))
2885+
I->setIsDisjoint(Disjoint);
2886+
cast<PossiblyDisjointInst>(NewBO)->setIsDisjoint(Disjoint);
28802887
}
28812888

28822889
BO->replaceAllUsesWith(NewBO);

‎llvm/test/CodeGen/AArch64/GlobalISel/knownbits-buildvector.mir‎

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
3+
4+
---
5+
name: const
6+
body: |
7+
bb.1:
8+
; CHECK-LABEL: name: @const
9+
; CHECK-NEXT: %0:_ KnownBits:00000011 SignBits:6
10+
; CHECK-NEXT: %1:_ KnownBits:00001010 SignBits:4
11+
; CHECK-NEXT: %2:_ KnownBits:0000?01? SignBits:4
12+
%0:_(s8) = G_CONSTANT i8 3
13+
%1:_(s8) = G_CONSTANT i8 10
14+
%2:_(<2 x s8>) = G_BUILD_VECTOR %0, %1
15+
...
16+
---
17+
name: const_lane1
18+
body: |
19+
bb.1:
20+
; CHECK-LABEL: name: @const_lane1
21+
; CHECK-NEXT: %0:_ KnownBits:00000011 SignBits:6
22+
; CHECK-NEXT: %1:_ KnownBits:00001010 SignBits:4
23+
; CHECK-NEXT: %2:_ KnownBits:0000?01? SignBits:4
24+
; CHECK-NEXT: %idx:_ KnownBits:0000000000000000000000000000000000000000000000000000000000000001 SignBits:63
25+
; CHECK-NEXT: %4:_ KnownBits:???????? SignBits:1
26+
%0:_(s8) = G_CONSTANT i8 3
27+
%1:_(s8) = G_CONSTANT i8 10
28+
%2:_(<2 x s8>) = G_BUILD_VECTOR %0, %1
29+
%idx:_(s64) = G_CONSTANT i64 1
30+
%3:_(s8) = G_EXTRACT_VECTOR_ELT %2, %idx
31+
...
32+
---
33+
name: sextsignbits
34+
body: |
35+
bb.1:
36+
; CHECK-LABEL: name: @sextsignbits
37+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
38+
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
39+
; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:25
40+
; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:17
41+
; CHECK-NEXT: %4:_ KnownBits:???????????????????????????????? SignBits:17
42+
%0:_(s8) = COPY $b0
43+
%1:_(s16) = COPY $h1
44+
%2:_(s32) = G_SEXT %0
45+
%3:_(s32) = G_SEXT %1
46+
%4:_(<2 x s32>) = G_BUILD_VECTOR %2, %3
47+
...
48+
---
49+
name: sextsignbits_lane1
50+
body: |
51+
bb.1:
52+
; CHECK-LABEL: name: @sextsignbits_lane1
53+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
54+
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
55+
; CHECK-NEXT: %2:_ KnownBits:???????????????????????????????? SignBits:25
56+
; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:17
57+
; CHECK-NEXT: %4:_ KnownBits:???????????????????????????????? SignBits:17
58+
; CHECK-NEXT: %idx:_ KnownBits:0000000000000000000000000000000000000000000000000000000000000001 SignBits:63
59+
; CHECK-NEXT: %6:_ KnownBits:???????????????????????????????? SignBits:1
60+
%0:_(s8) = COPY $b0
61+
%1:_(s16) = COPY $h1
62+
%2:_(s32) = G_SEXT %0
63+
%3:_(s32) = G_SEXT %1
64+
%4:_(<2 x s32>) = G_BUILD_VECTOR %2, %3
65+
%idx:_(s64) = G_CONSTANT i64 1
66+
%5:_(s32) = G_EXTRACT_VECTOR_ELT %4, %idx
67+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shuffle.mir‎

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -filetype=null 2>&1 | FileCheck %s
3+
4+
---
5+
name: lane0
6+
body: |
7+
bb.1:
8+
; CHECK-LABEL: name: @lane0
9+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
10+
; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
11+
; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
12+
%0:_(<2 x s8>) = COPY $h0
13+
%1:_(<2 x s8>) = COPY $h1
14+
%2:_(<2 x s8>) = G_SHUFFLE_VECTOR %0, %1, shufflemask(0, 0)
15+
...
16+
---
17+
name: zext_known
18+
body: |
19+
bb.1:
20+
; CHECK-LABEL: name: @zext_known
21+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
22+
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
23+
; CHECK-NEXT: %2:_ KnownBits:00000000???????? SignBits:8
24+
; CHECK-NEXT: %3:_ KnownBits:00000000???????? SignBits:8
25+
%0:_(<2 x s8>) = COPY $h0
26+
%1:_(<2 x s16>) = COPY $s1
27+
%2:_(<2 x s16>) = G_ZEXT %0
28+
%3:_(<2 x s16>) = G_SHUFFLE_VECTOR %2, %1, shufflemask(0, 0)
29+
...
30+
---
31+
name: zext_unknown
32+
body: |
33+
bb.1:
34+
; CHECK-LABEL: name: @zext_unknown
35+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
36+
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
37+
; CHECK-NEXT: %2:_ KnownBits:00000000???????? SignBits:8
38+
; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
39+
%0:_(<2 x s8>) = COPY $h0
40+
%1:_(<2 x s16>) = COPY $s1
41+
%2:_(<2 x s16>) = G_ZEXT %0
42+
%3:_(<2 x s16>) = G_SHUFFLE_VECTOR %2, %1, shufflemask(0, 2)
43+
...
44+
---
45+
name: sext_known
46+
body: |
47+
bb.1:
48+
; CHECK-LABEL: name: @sext_known
49+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
50+
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
51+
; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:9
52+
; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
53+
%0:_(<2 x s8>) = COPY $h0
54+
%1:_(<2 x s16>) = COPY $s1
55+
%2:_(<2 x s16>) = G_SEXT %0
56+
%3:_(<2 x s16>) = G_SHUFFLE_VECTOR %2, %1, shufflemask(0, 0)
57+
...
58+
---
59+
name: sext_unknown
60+
body: |
61+
bb.1:
62+
; CHECK-LABEL: name: @sext_unknown
63+
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
64+
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
65+
; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:9
66+
; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
67+
%0:_(<2 x s8>) = COPY $h0
68+
%1:_(<2 x s16>) = COPY $s1
69+
%2:_(<2 x s16>) = G_SEXT %0
70+
%3:_(<2 x s16>) = G_SHUFFLE_VECTOR %2, %1, shufflemask(0, 2)
71+
...

‎llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll‎

Lines changed: 15 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -38,9 +38,9 @@ define <8 x i16> @dupzext_v8i8_v8i16(i8 %src, <8 x i8> %b) {
3838
; CHECK-GI-LABEL: dupzext_v8i8_v8i16:
3939
; CHECK-GI: // %bb.0: // %entry
4040
; CHECK-GI-NEXT: and w8, w0, #0xff
41-
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
4241
; CHECK-GI-NEXT: dup v1.8h, w8
43-
; CHECK-GI-NEXT: mul v0.8h, v1.8h, v0.8h
42+
; CHECK-GI-NEXT: xtn v1.8b, v1.8h
43+
; CHECK-GI-NEXT: umull v0.8h, v1.8b, v0.8b
4444
; CHECK-GI-NEXT: ret
4545
entry:
4646
%in = zext i8 %src to i16
@@ -84,9 +84,9 @@ define <4 x i32> @dupzext_v4i16_v4i32(i16 %src, <4 x i16> %b) {
8484
; CHECK-GI-LABEL: dupzext_v4i16_v4i32:
8585
; CHECK-GI: // %bb.0: // %entry
8686
; CHECK-GI-NEXT: and w8, w0, #0xffff
87-
; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0
8887
; CHECK-GI-NEXT: dup v1.4s, w8
89-
; CHECK-GI-NEXT: mul v0.4s, v1.4s, v0.4s
88+
; CHECK-GI-NEXT: xtn v1.4h, v1.4s
89+
; CHECK-GI-NEXT: umull v0.4s, v1.4h, v0.4h
9090
; CHECK-GI-NEXT: ret
9191
entry:
9292
%in = zext i16 %src to i32
@@ -138,16 +138,9 @@ define <2 x i64> @dupzext_v2i32_v2i64(i32 %src, <2 x i32> %b) {
138138
; CHECK-GI-LABEL: dupzext_v2i32_v2i64:
139139
; CHECK-GI: // %bb.0: // %entry
140140
; CHECK-GI-NEXT: mov w8, w0
141-
; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0
142141
; CHECK-GI-NEXT: dup v1.2d, x8
143-
; CHECK-GI-NEXT: fmov x9, d0
144-
; CHECK-GI-NEXT: mov x11, v0.d[1]
145-
; CHECK-GI-NEXT: fmov x8, d1
146-
; CHECK-GI-NEXT: mov x10, v1.d[1]
147-
; CHECK-GI-NEXT: mul x8, x8, x9
148-
; CHECK-GI-NEXT: mul x9, x10, x11
149-
; CHECK-GI-NEXT: mov v0.d[0], x8
150-
; CHECK-GI-NEXT: mov v0.d[1], x9
142+
; CHECK-GI-NEXT: xtn v1.2s, v1.2d
143+
; CHECK-GI-NEXT: umull v0.2d, v1.2s, v0.2s
151144
; CHECK-GI-NEXT: ret
152145
entry:
153146
%in = zext i32 %src to i64
@@ -169,16 +162,9 @@ define <2 x i32> @dupzext_v2i32_v2i64_trunc(i32 %src, <2 x i32> %b) {
169162
; CHECK-GI-LABEL: dupzext_v2i32_v2i64_trunc:
170163
; CHECK-GI: // %bb.0: // %entry
171164
; CHECK-GI-NEXT: mov w8, w0
172-
; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0
173165
; CHECK-GI-NEXT: dup v1.2d, x8
174-
; CHECK-GI-NEXT: fmov x9, d0
175-
; CHECK-GI-NEXT: mov x11, v0.d[1]
176-
; CHECK-GI-NEXT: fmov x8, d1
177-
; CHECK-GI-NEXT: mov x10, v1.d[1]
178-
; CHECK-GI-NEXT: mul x8, x8, x9
179-
; CHECK-GI-NEXT: mul x9, x10, x11
180-
; CHECK-GI-NEXT: mov v0.d[0], x8
181-
; CHECK-GI-NEXT: mov v0.d[1], x9
166+
; CHECK-GI-NEXT: xtn v1.2s, v1.2d
167+
; CHECK-GI-NEXT: umull v0.2d, v1.2s, v0.2s
182168
; CHECK-GI-NEXT: xtn v0.2s, v0.2d
183169
; CHECK-GI-NEXT: ret
184170
entry:
@@ -240,14 +226,9 @@ define <2 x i64> @dupzext_v2i16_v2i64(i16 %src, <2 x i16> %b) {
240226
; CHECK-GI-NEXT: and x8, x0, #0xffff
241227
; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b
242228
; CHECK-GI-NEXT: dup v1.2d, x8
243-
; CHECK-GI-NEXT: fmov x8, d1
244-
; CHECK-GI-NEXT: fmov x9, d0
245-
; CHECK-GI-NEXT: mov x10, v1.d[1]
246-
; CHECK-GI-NEXT: mov x11, v0.d[1]
247-
; CHECK-GI-NEXT: mul x8, x8, x9
248-
; CHECK-GI-NEXT: mul x9, x10, x11
249-
; CHECK-GI-NEXT: mov v0.d[0], x8
250-
; CHECK-GI-NEXT: mov v0.d[1], x9
229+
; CHECK-GI-NEXT: xtn v1.2s, v1.2d
230+
; CHECK-GI-NEXT: xtn v0.2s, v0.2d
231+
; CHECK-GI-NEXT: umull v0.2d, v1.2s, v0.2s
251232
; CHECK-GI-NEXT: ret
252233
entry:
253234
%in = zext i16 %src to i64
@@ -491,10 +472,10 @@ define <8 x i16> @shufzext_v8i8_v8i16(<8 x i8> %src, <8 x i8> %b) {
491472
; CHECK-GI-LABEL: shufzext_v8i8_v8i16:
492473
; CHECK-GI: // %bb.0: // %entry
493474
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
494-
; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
495475
; CHECK-GI-NEXT: rev64 v0.8h, v0.8h
496476
; CHECK-GI-NEXT: ext v0.16b, v0.16b, v0.16b, #8
497-
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
477+
; CHECK-GI-NEXT: xtn v0.8b, v0.8h
478+
; CHECK-GI-NEXT: umull v0.8h, v0.8b, v1.8b
498479
; CHECK-GI-NEXT: ret
499480
entry:
500481
%in = zext <8 x i8> %src to <8 x i16>
@@ -545,8 +526,8 @@ define <8 x i16> @shufzext_v8i8_v8i16_twoin(<8 x i8> %src1, <8 x i8> %src2, <8 x
545526
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
546527
; CHECK-GI-NEXT: ushll v1.8h, v1.8b, #0
547528
; CHECK-GI-NEXT: trn1 v0.8h, v0.8h, v1.8h
548-
; CHECK-GI-NEXT: ushll v1.8h, v2.8b, #0
549-
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
529+
; CHECK-GI-NEXT: xtn v0.8b, v0.8h
530+
; CHECK-GI-NEXT: umull v0.8h, v0.8b, v2.8b
550531
; CHECK-GI-NEXT: ret
551532
entry:
552533
%in1 = zext <8 x i8> %src1 to <8 x i16>

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