[AMDGPU] Add off-by-default flag to control LiveRegOpt

Change-Id: Id939bf74b48b47e5ee2b432956e476fac80e3375

Author: jrbyrnes

llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp

@@ -321,7 +321,8 @@ unsigned GCNTTIImpl::getNumberOfParts(Type *Tp) {
   // queries (e.g. get*InstrCost) to decide the proper handling
   // of 8 bit vectors.
   if (FixedVectorType *VTy = dyn_cast<FixedVectorType>(Tp)) {
-    if (DL.getTypeSizeInBits(VTy->getElementType()) == 8) {
+    if (ST->shouldCoerceIllegalTypes() &&
+        DL.getTypeSizeInBits(VTy->getElementType()) == 8) {
       unsigned ElCount = VTy->getElementCount().getFixedValue();
       return PowerOf2Ceil(ElCount / 4);
     }
@@ -362,10 +363,10 @@ unsigned GCNTTIImpl::getMaximumVF(unsigned ElemWidth, unsigned Opcode) const {
   if (Opcode == Instruction::Load || Opcode == Instruction::Store)
     return 32 * 4 / ElemWidth;
 
-  return (ElemWidth == 8)                              ? 4
-         : (ElemWidth == 16)                           ? 2
-         : (ElemWidth == 32 && ST->hasPackedFP32Ops()) ? 2
-                                                       : 1;
+  return (ST->shouldCoerceIllegalTypes() && ElemWidth == 8) ? 4
+         : (ElemWidth == 16)                                ? 2
+         : (ElemWidth == 32 && ST->hasPackedFP32Ops())      ? 2
+                                                            : 1;
 }
 
 unsigned GCNTTIImpl::getLoadVectorFactor(unsigned VF, unsigned LoadSize,
@@ -1175,7 +1176,8 @@ InstructionCost GCNTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
 
   unsigned ScalarSize = DL.getTypeSizeInBits(VT->getElementType());
   if (ST->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
-      (ScalarSize == 16 || ScalarSize == 8)) {
+      (ScalarSize == 16 ||
+       (ScalarSize == 8 && ST->shouldCoerceIllegalTypes()))) {
     // Larger vector widths may require additional instructions, but are
     // typically cheaper than scalarized versions.
     unsigned NumVectorElts = cast<FixedVectorType>(VT)->getNumElements();

llvm/lib/Target/AMDGPU/GCNSubtarget.cpp

@@ -52,6 +52,11 @@ static cl::opt<unsigned>
                  cl::desc("Number of addresses from which to enable MIMG NSA."),
                  cl::init(2), cl::Hidden);
 
+static cl::opt<bool>
+    CoerceIllegal("amdgpu-coerce-illegal-types",
+                  cl::desc("Whether or not to coerce illegal types"),
+                  cl::ReallyHidden, cl::init(false));
+
 GCNSubtarget::~GCNSubtarget() = default;
 
 GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT,
@@ -191,6 +196,8 @@ GCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
   RegBankInfo = std::make_unique<AMDGPURegisterBankInfo>(*this);
   InstSelector =
       std::make_unique<AMDGPUInstructionSelector>(*this, *RegBankInfo, TM);
+
+  ShouldCoerceIllegalTypes = CoerceIllegal;
 }
 
 const SelectionDAGTargetInfo *GCNSubtarget::getSelectionDAGInfo() const {

llvm/lib/Target/AMDGPU/GCNSubtarget.h

@@ -259,6 +259,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
   // Dummy feature to use for assembler in tablegen.
   bool FeatureDisable = false;
 
+  bool ShouldCoerceIllegalTypes = false;
+
 private:
   SIInstrInfo InstrInfo;
   SITargetLowering TLInfo;
@@ -1445,6 +1447,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
   // of sign-extending.
   bool hasGetPCZeroExtension() const { return GFX12Insts; }
 
+  /// \returns whether or not we should coerce illegal types into vectors of
+  // legal types for values that span basic blocks.
+  bool shouldCoerceIllegalTypes() const { return ShouldCoerceIllegalTypes; }
+
   /// \returns SGPR allocation granularity supported by the subtarget.
   unsigned getSGPRAllocGranule() const {
     return AMDGPU::IsaInfo::getSGPRAllocGranule(this);