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[SPARC] Use fzero/fzeros to materialize FP zeros when we have VIS
Reviewers: rorth, brad0, s-barannikov Reviewed By: s-barannikov Pull Request: llvm#135712
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4 files changed

+139
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‎llvm/lib/Target/Sparc/SparcISelLowering.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3560,6 +3560,12 @@ bool SparcTargetLowering::useLoadStackGuardNode(const Module &M) const {
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return true;
35613561
}
35623562

3563+
bool SparcTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
3564+
bool ForCodeSize) const {
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return Subtarget->isVIS() && (VT == MVT::f32 || VT == MVT::f64) &&
3566+
Imm.isZero();
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}
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35633569
// Override to disable global variable loading on Linux.
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void SparcTargetLowering::insertSSPDeclarations(Module &M) const {
35653571
if (!Subtarget->isTargetLinux())

‎llvm/lib/Target/Sparc/SparcISelLowering.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -207,6 +207,9 @@ namespace llvm {
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return VT != MVT::f128;
208208
}
209209

210+
bool isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const override;
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210213
bool shouldInsertFencesForAtomic(const Instruction *I) const override {
211214
// FIXME: We insert fences for each atomics and generate
212215
// sub-optimal code for PSO/TSO. (Approximately nobody uses any

‎llvm/lib/Target/Sparc/SparcInstrVIS.td

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,10 +45,10 @@ class VISInst2<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
4545
!strconcat(OpcStr, " $rs2, $rd")>;
4646

4747
// For VIS Instructions with only rd operand.
48-
let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
48+
let rs1 = 0, rs2 = 0 in
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class VISInstD<bits<9> opfval, string OpcStr, RegisterClass RC = DFPRegs>
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: VISInstFormat<opfval,
51-
(outs RC:$rd), (ins RC:$f),
51+
(outs RC:$rd), (ins),
5252
!strconcat(OpcStr, " $rd")>;
5353

5454
// VIS 1 Instructions
@@ -277,3 +277,16 @@ def UMULXHI : VISInst<0b000010110, "umulxhi", I64Regs>;
277277
def XMULX : VISInst<0b100010101, "xmulx", I64Regs>;
278278
def XMULXHI : VISInst<0b100010110, "xmulxhi", I64Regs>;
279279
} // Predicates = [IsVIS3]
280+
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// FP immediate patterns.
282+
def fpimm0 : FPImmLeaf<fAny, [{return Imm.isExactlyValue(+0.0);}]>;
283+
def fpnegimm0 : FPImmLeaf<fAny, [{return Imm.isExactlyValue(-0.0);}]>;
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// VIS instruction patterns.
286+
let Predicates = [HasVIS] in {
287+
// Zero immediate.
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def : Pat<(f64 fpimm0), (FZERO)>;
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def : Pat<(f32 fpimm0), (FZEROS)>;
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def : Pat<(f64 fpnegimm0), (FNEGD (FZERO))>;
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def : Pat<(f32 fpnegimm0), (FNEGS (FZEROS))>;
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} // Predicates = [HasVIS]

‎llvm/test/CodeGen/SPARC/float-constants.ll

Lines changed: 115 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
22
; RUN: llc < %s -mtriple=sparc | FileCheck %s
33
; RUN: llc < %s -mtriple=sparcel | FileCheck %s --check-prefix=CHECK-LE
4+
; RUN: llc < %s -mtriple=sparcv9 -mattr=+vis | FileCheck %s --check-prefix=CHECK-VIS
45

56
;; Bitcast should not do a runtime conversion, but rather emit a
67
;; constant into integer registers directly.
@@ -17,6 +18,12 @@ define <2 x i32> @bitcast() nounwind {
1718
; CHECK-LE-NEXT: sethi 1049856, %o1
1819
; CHECK-LE-NEXT: retl
1920
; CHECK-LE-NEXT: mov %g0, %o0
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;
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; CHECK-VIS-LABEL: bitcast:
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; CHECK-VIS: ! %bb.0:
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; CHECK-VIS-NEXT: sethi 1049856, %o0
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; CHECK-VIS-NEXT: retl
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; CHECK-VIS-NEXT: mov %g0, %o1
2027
%1 = bitcast double 5.0 to <2 x i32>
2128
ret <2 x i32> %1
2229
}
@@ -43,6 +50,17 @@ define void @test_call() nounwind {
4350
; CHECK-LE-NEXT: mov %g0, %o0
4451
; CHECK-LE-NEXT: ret
4552
; CHECK-LE-NEXT: restore
53+
;
54+
; CHECK-VIS-LABEL: test_call:
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; CHECK-VIS: ! %bb.0:
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; CHECK-VIS-NEXT: save %sp, -176, %sp
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; CHECK-VIS-NEXT: sethi %h44(.LCPI1_0), %i0
58+
; CHECK-VIS-NEXT: add %i0, %m44(.LCPI1_0), %i0
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; CHECK-VIS-NEXT: sllx %i0, 12, %i0
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; CHECK-VIS-NEXT: call a
61+
; CHECK-VIS-NEXT: ldd [%i0+%l44(.LCPI1_0)], %f0
62+
; CHECK-VIS-NEXT: ret
63+
; CHECK-VIS-NEXT: restore
4664
call void @a(double 5.0)
4765
ret void
4866
}
@@ -75,6 +93,103 @@ define double @test_intrins_call() nounwind {
7593
; CHECK-LE-NEXT: mov %o1, %o3
7694
; CHECK-LE-NEXT: ret
7795
; CHECK-LE-NEXT: restore
96+
;
97+
; CHECK-VIS-LABEL: test_intrins_call:
98+
; CHECK-VIS: ! %bb.0:
99+
; CHECK-VIS-NEXT: save %sp, -176, %sp
100+
; CHECK-VIS-NEXT: sethi %h44(.LCPI2_0), %i0
101+
; CHECK-VIS-NEXT: add %i0, %m44(.LCPI2_0), %i0
102+
; CHECK-VIS-NEXT: sllx %i0, 12, %i0
103+
; CHECK-VIS-NEXT: ldd [%i0+%l44(.LCPI2_0)], %f0
104+
; CHECK-VIS-NEXT: fmovd %f0, %f2
105+
; CHECK-VIS-NEXT: call pow
106+
; CHECK-VIS-NEXT: nop
107+
; CHECK-VIS-NEXT: ret
108+
; CHECK-VIS-NEXT: restore
78109
%1 = call double @llvm.pow.f64(double 2.0, double 2.0)
79110
ret double %1
80111
}
112+
113+
;; When we have VIS, f32/f64 zero constant should be materialized from fzero/fzeros.
114+
115+
define double @pos_zero_double() nounwind {
116+
; CHECK-LABEL: pos_zero_double:
117+
; CHECK: ! %bb.0:
118+
; CHECK-NEXT: sethi %hi(.LCPI3_0), %o0
119+
; CHECK-NEXT: retl
120+
; CHECK-NEXT: ldd [%o0+%lo(.LCPI3_0)], %f0
121+
;
122+
; CHECK-LE-LABEL: pos_zero_double:
123+
; CHECK-LE: ! %bb.0:
124+
; CHECK-LE-NEXT: sethi %hi(.LCPI3_0), %o0
125+
; CHECK-LE-NEXT: retl
126+
; CHECK-LE-NEXT: ldd [%o0+%lo(.LCPI3_0)], %f0
127+
;
128+
; CHECK-VIS-LABEL: pos_zero_double:
129+
; CHECK-VIS: ! %bb.0:
130+
; CHECK-VIS-NEXT: retl
131+
; CHECK-VIS-NEXT: fzero %f0
132+
ret double +0.0
133+
}
134+
135+
define double @neg_zero_double() nounwind {
136+
; CHECK-LABEL: neg_zero_double:
137+
; CHECK: ! %bb.0:
138+
; CHECK-NEXT: sethi %hi(.LCPI4_0), %o0
139+
; CHECK-NEXT: retl
140+
; CHECK-NEXT: ldd [%o0+%lo(.LCPI4_0)], %f0
141+
;
142+
; CHECK-LE-LABEL: neg_zero_double:
143+
; CHECK-LE: ! %bb.0:
144+
; CHECK-LE-NEXT: sethi %hi(.LCPI4_0), %o0
145+
; CHECK-LE-NEXT: retl
146+
; CHECK-LE-NEXT: ldd [%o0+%lo(.LCPI4_0)], %f0
147+
;
148+
; CHECK-VIS-LABEL: neg_zero_double:
149+
; CHECK-VIS: ! %bb.0:
150+
; CHECK-VIS-NEXT: fzero %f0
151+
; CHECK-VIS-NEXT: retl
152+
; CHECK-VIS-NEXT: fnegd %f0, %f0
153+
ret double -0.0
154+
}
155+
156+
define float @pos_zero_float() nounwind {
157+
; CHECK-LABEL: pos_zero_float:
158+
; CHECK: ! %bb.0:
159+
; CHECK-NEXT: sethi %hi(.LCPI5_0), %o0
160+
; CHECK-NEXT: retl
161+
; CHECK-NEXT: ld [%o0+%lo(.LCPI5_0)], %f0
162+
;
163+
; CHECK-LE-LABEL: pos_zero_float:
164+
; CHECK-LE: ! %bb.0:
165+
; CHECK-LE-NEXT: sethi %hi(.LCPI5_0), %o0
166+
; CHECK-LE-NEXT: retl
167+
; CHECK-LE-NEXT: ld [%o0+%lo(.LCPI5_0)], %f0
168+
;
169+
; CHECK-VIS-LABEL: pos_zero_float:
170+
; CHECK-VIS: ! %bb.0:
171+
; CHECK-VIS-NEXT: retl
172+
; CHECK-VIS-NEXT: fzeros %f0
173+
ret float +0.0
174+
}
175+
176+
define float @neg_zero_float() nounwind {
177+
; CHECK-LABEL: neg_zero_float:
178+
; CHECK: ! %bb.0:
179+
; CHECK-NEXT: sethi %hi(.LCPI6_0), %o0
180+
; CHECK-NEXT: retl
181+
; CHECK-NEXT: ld [%o0+%lo(.LCPI6_0)], %f0
182+
;
183+
; CHECK-LE-LABEL: neg_zero_float:
184+
; CHECK-LE: ! %bb.0:
185+
; CHECK-LE-NEXT: sethi %hi(.LCPI6_0), %o0
186+
; CHECK-LE-NEXT: retl
187+
; CHECK-LE-NEXT: ld [%o0+%lo(.LCPI6_0)], %f0
188+
;
189+
; CHECK-VIS-LABEL: neg_zero_float:
190+
; CHECK-VIS: ! %bb.0:
191+
; CHECK-VIS-NEXT: fzeros %f0
192+
; CHECK-VIS-NEXT: retl
193+
; CHECK-VIS-NEXT: fnegs %f0, %f0
194+
ret float -0.0
195+
}

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