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Add builtin/intrinsic global_(load|store)_b128 (llvm#4455)
_(This is a consolidation of PR llvm#4213 which went through numerous revisions and accumulated quite a bit of noise.)_ Associated JIRA: [SWDEV-556587](https://ontrack-internal.amd.com/browse/SWDEV-556587) Add clang builtin for system-scoped store of 128bits New clang builtins: 1. `__builtin_amdgcn_global_load_b128` - Example usage: [clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl:57](https://github.com/AMD-Lightning-Internal/llvm-project/blob/amd/dev/macurtis/swdev/553136/draft-0910/clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl#L57) - Generates intrinsic `llvm.amdgcn.global.load.b128` - [llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.b128.ll:23](https://github.com/AMD-Lightning-Internal/llvm-project/tree/amd/dev/macurtis/swdev/553136/draft-0910/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.load.b128.ll#L23) 2. `__builtin_amdgcn_global_store_b128` - Example usage: [clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl:18](https://github.com/AMD-Lightning-Internal/llvm-project/blob/amd/dev/macurtis/swdev/553136/draft-0910/clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl#L18) - Generates intrinsic `llvm.amdgcn.global.store.b128` - [llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.b128.ll:22](https://github.com/AMD-Lightning-Internal/llvm-project/tree/amd/dev/macurtis/swdev/553136/draft-0910/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.store.b128.ll#L22) Co-authored-by: Matthew Curtis <macurtis@amd.com>
1 parent aaa1220 commit 144d547

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‎clang/docs/LanguageExtensions.rst‎

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@@ -5324,6 +5324,53 @@ returns the bit at the position of the current lane. It is almost equivalent to
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``(mask & (1 << lane_id)) != 0``, except that its behavior is only defined if
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the given mask has the same value for all active lanes of the current wave.
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__builtin_amdgcn_global_load_b128 and __builtin_amdgcn_global_store_b128
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Signature:
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.. code-block:: c
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typedef __attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int v4u;
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typedef v4u __attribute__((address_space(1))) *global_ptr_to_v4u;
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v4u __builtin_amdgcn_global_load_b128(
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v4u __attribute__((address_space(1))) *src,
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const char *scope);
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void __builtin_amdgcn_global_store_b128(
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v4u __attribute__((address_space(1))) *dst,
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v4u data,
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const char *scope);
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Load or store a vector of 4 unsigned integers from or to global memory with
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cache behavior specified by `scope` which must be a string literal.
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Valid values for `scope` are:
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===================== ==========================================================
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scope architecture name
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===================== ==========================================================
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``"wavefront"`` wave
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``"workgroup"`` group
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``"agent"`` device
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``""`` (empty string) system
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===================== ==========================================================
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These builtins are only supported on gfx942 and gfx950 devices.
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For semantics on gfx942, see Tables 47 and 48 in section 9.1.10 "Memory Scope
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and Temporal Controls" of the "AMD Instinct MI300" Instruction Set Architecture
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Reference.
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For semantics on gfx950, see Tables 49 and 50 in section 9.1.10 "Memory Scope
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and Temporal Controls" of the CDNA4 Instruction Set Architecture Reference.
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ARM/AArch64 Language Extensions
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-------------------------------
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‎clang/include/clang/Basic/BuiltinsAMDGPU.def‎

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@@ -190,6 +190,9 @@ TARGET_BUILTIN(__builtin_amdgcn_raw_ptr_buffer_atomic_fmax_f64, "ddQbiiIi", "t",
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TARGET_BUILTIN(__builtin_amdgcn_raw_ptr_buffer_load_lds, "vQbv*3IUiiiIiIi", "t", "vmem-to-lds-load-insts")
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TARGET_BUILTIN(__builtin_amdgcn_struct_ptr_buffer_load_lds, "vQbv*3IUiiiiIiIi", "t", "vmem-to-lds-load-insts")
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TARGET_BUILTIN(__builtin_amdgcn_global_load_b128, "V4UiV4Ui*1cC*", "n", "gfx940-insts")
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TARGET_BUILTIN(__builtin_amdgcn_global_store_b128, "vV4Ui*1V4UicC*", "n", "gfx940-insts")
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//===----------------------------------------------------------------------===//
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// Ballot builtins.
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//===----------------------------------------------------------------------===//

‎clang/include/clang/Sema/SemaAMDGPU.h‎

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@@ -32,6 +32,8 @@ class SemaAMDGPU : public SemaBase {
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bool checkCoopAtomicFunctionCall(CallExpr *TheCall, bool IsStore);
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bool checkScopedMemAccessFunctionCall(CallExpr *TheCall);
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bool checkMovDPPFunctionCall(CallExpr *TheCall, unsigned NumArgs,
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unsigned NumDataArgs);
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‎clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp‎

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@@ -830,6 +830,26 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
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llvm::Function *F = CGM.getIntrinsic(IID, {Args[0]->getType()});
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return Builder.CreateCall(F, {Args});
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}
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case AMDGPU::BI__builtin_amdgcn_global_load_b128:
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case AMDGPU::BI__builtin_amdgcn_global_store_b128: {
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const bool IsStore =
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BuiltinID == AMDGPU::BI__builtin_amdgcn_global_store_b128;
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LLVMContext &Ctx = CGM.getLLVMContext();
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SmallVector<Value *, 5> Args = {EmitScalarExpr(E->getArg(0))}; // addr
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if (IsStore)
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Args.push_back(EmitScalarExpr(E->getArg(1))); // data
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const unsigned ScopeIdx = E->getNumArgs() - 1;
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StringRef ScopeLit =
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cast<StringLiteral>(E->getArg(ScopeIdx)->IgnoreParenCasts())
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->getString();
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llvm::MDNode *MD =
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llvm::MDNode::get(Ctx, {llvm::MDString::get(Ctx, ScopeLit)});
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Args.push_back(llvm::MetadataAsValue::get(Ctx, MD)); // scope
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llvm::Function *F =
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CGM.getIntrinsic(IsStore ? Intrinsic::amdgcn_global_store_b128
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: Intrinsic::amdgcn_global_load_b128);
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return Builder.CreateCall(F, Args);
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}
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case AMDGPU::BI__builtin_amdgcn_get_fpenv: {
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Function *F = CGM.getIntrinsic(Intrinsic::get_fpenv,
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{llvm::Type::getInt64Ty(getLLVMContext())});

‎clang/lib/Sema/SemaAMDGPU.cpp‎

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@@ -112,6 +112,9 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned BuiltinID,
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case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_store_16x8B:
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case AMDGPU::BI__builtin_amdgcn_cooperative_atomic_store_8x16B:
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return checkCoopAtomicFunctionCall(TheCall, /*IsStore=*/true);
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case AMDGPU::BI__builtin_amdgcn_global_load_b128:
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case AMDGPU::BI__builtin_amdgcn_global_store_b128:
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return checkScopedMemAccessFunctionCall(TheCall);
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default:
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return false;
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}
@@ -201,6 +204,19 @@ bool SemaAMDGPU::checkCoopAtomicFunctionCall(CallExpr *TheCall, bool IsStore) {
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return Fail;
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}
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bool SemaAMDGPU::checkScopedMemAccessFunctionCall(CallExpr *TheCall) {
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bool Fail = false;
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// Last argument is a string literal
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Expr *Arg = TheCall->getArg(TheCall->getNumArgs() - 1);
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auto Scope = dyn_cast<StringLiteral>(Arg->IgnoreParenCasts());
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if (!Scope) {
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Fail = true;
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Diag(TheCall->getBeginLoc(), diag::err_expr_not_string_literal)
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<< Arg->getSourceRange();
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}
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return Fail;
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}
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bool SemaAMDGPU::checkMovDPPFunctionCall(CallExpr *TheCall, unsigned NumArgs,
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unsigned NumDataArgs) {
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assert(NumDataArgs <= 2);

‎clang/test/CodeGenOpenCL/builtins-amdgcn-global-load-store.cl‎

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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals smart
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// REQUIRES: amdgpu-registered-target
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx950 -emit-llvm -o - %s | FileCheck %s -check-prefixes=GFX,GFX950
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx9-4-generic -emit-llvm -o - %s | FileCheck %s -check-prefixes=GFX,GFX9_4_GENERIC
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typedef __attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int v4u32;
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typedef v4u32 __global *global_ptr_to_v4u32;
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//------------------------------------------------------------------------------
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// Store
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//------------------------------------------------------------------------------
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// GFX-LABEL: @test_amdgcn_global_store_b128_00(
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// GFX-NEXT: entry:
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// GFX-NEXT: tail call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) [[PTR:%.*]], <4 x i32> [[DATA:%.*]], metadata [[META4:![0-9]+]])
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// GFX-NEXT: ret void
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//
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void test_amdgcn_global_store_b128_00(global_ptr_to_v4u32 ptr, v4u32 data) {
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__builtin_amdgcn_global_store_b128(ptr, data, "wavefront");
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}
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// GFX-LABEL: @test_amdgcn_global_store_b128_01(
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// GFX-NEXT: entry:
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// GFX-NEXT: tail call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) [[PTR:%.*]], <4 x i32> [[DATA:%.*]], metadata [[META5:![0-9]+]])
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// GFX-NEXT: ret void
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//
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void test_amdgcn_global_store_b128_01(global_ptr_to_v4u32 ptr, v4u32 data) {
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__builtin_amdgcn_global_store_b128(ptr, data, "workgroup");
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}
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// GFX-LABEL: @test_amdgcn_global_store_b128_10(
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// GFX-NEXT: entry:
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// GFX-NEXT: tail call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) [[PTR:%.*]], <4 x i32> [[DATA:%.*]], metadata [[META6:![0-9]+]])
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// GFX-NEXT: ret void
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//
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void test_amdgcn_global_store_b128_10(global_ptr_to_v4u32 ptr, v4u32 data) {
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__builtin_amdgcn_global_store_b128(ptr, data, "agent");
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}
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// GFX-LABEL: @test_amdgcn_global_store_b128_11(
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// GFX-NEXT: entry:
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// GFX-NEXT: tail call void @llvm.amdgcn.global.store.b128(ptr addrspace(1) [[PTR:%.*]], <4 x i32> [[DATA:%.*]], metadata [[META7:![0-9]+]])
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// GFX-NEXT: ret void
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//
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void test_amdgcn_global_store_b128_11(global_ptr_to_v4u32 ptr, v4u32 data) {
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__builtin_amdgcn_global_store_b128(ptr, data, "");
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}
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//------------------------------------------------------------------------------
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// Load
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//------------------------------------------------------------------------------
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// GFX-LABEL: @test_amdgcn_global_load_b128_00(
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// GFX-NEXT: entry:
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// GFX-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) [[PTR:%.*]], metadata [[META4]])
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// GFX-NEXT: ret <4 x i32> [[TMP0]]
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//
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v4u32 test_amdgcn_global_load_b128_00(global_ptr_to_v4u32 ptr) {
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return __builtin_amdgcn_global_load_b128(ptr, "wavefront");
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}
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// GFX-LABEL: @test_amdgcn_global_load_b128_01(
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// GFX-NEXT: entry:
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// GFX-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) [[PTR:%.*]], metadata [[META5]])
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// GFX-NEXT: ret <4 x i32> [[TMP0]]
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//
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v4u32 test_amdgcn_global_load_b128_01(global_ptr_to_v4u32 ptr) {
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return __builtin_amdgcn_global_load_b128(ptr, "workgroup");
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}
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// GFX-LABEL: @test_amdgcn_global_load_b128_10(
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// GFX-NEXT: entry:
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// GFX-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) [[PTR:%.*]], metadata [[META6]])
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// GFX-NEXT: ret <4 x i32> [[TMP0]]
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//
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v4u32 test_amdgcn_global_load_b128_10(global_ptr_to_v4u32 ptr) {
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return __builtin_amdgcn_global_load_b128(ptr, "agent");
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}
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// GFX-LABEL: @test_amdgcn_global_load_b128_11(
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// GFX-NEXT: entry:
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// GFX-NEXT: [[TMP0:%.*]] = tail call <4 x i32> @llvm.amdgcn.global.load.b128(ptr addrspace(1) [[PTR:%.*]], metadata [[META7]])
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// GFX-NEXT: ret <4 x i32> [[TMP0]]
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//
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v4u32 test_amdgcn_global_load_b128_11(global_ptr_to_v4u32 ptr) {
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return __builtin_amdgcn_global_load_b128(ptr, "");
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}
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//.
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// GFX950: [[META4]] = !{!"wavefront"}
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// GFX950: [[META5]] = !{!"workgroup"}
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// GFX950: [[META6]] = !{!"agent"}
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// GFX950: [[META7]] = !{!""}
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//.
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// GFX9_4_GENERIC: [[META4]] = !{!"wavefront"}
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// GFX9_4_GENERIC: [[META5]] = !{!"workgroup"}
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// GFX9_4_GENERIC: [[META6]] = !{!"agent"}
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// GFX9_4_GENERIC: [[META7]] = !{!""}
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//.
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//// NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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// GFX950: {{.*}}
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// GFX9_4_GENERIC: {{.*}}

‎clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-error.cl‎

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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx950 -S -verify -o - %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx9-4-generic -S -verify -o - %s
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// REQUIRES: amdgpu-registered-target
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typedef __attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int v4u32;
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typedef v4u32 __global *global_ptr_to_v4u32;
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void test_amdgcn_global_store_b128_00(v4u32 *ptr, v4u32 data, const char* scope) {
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__builtin_amdgcn_global_store_b128(ptr, data, ""); //expected-error{{passing '__private v4u32 *__private' to parameter of type '__attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int __global *' changes address space of pointer}}
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}
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void test_amdgcn_global_store_b128_01(global_ptr_to_v4u32 ptr, v4u32 data, const char* scope) {
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__builtin_amdgcn_global_store_b128(ptr, data, scope); //expected-error{{expression is not a string literal}}
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}
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v4u32 test_amdgcn_global_load_b128_00(v4u32 *ptr, const char* scope) {
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return __builtin_amdgcn_global_load_b128(ptr, ""); //expected-error{{passing '__private v4u32 *__private' to parameter of type '__attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int __global *' changes address space of pointer}}
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}
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v4u32 test_amdgcn_global_load_b128_01(global_ptr_to_v4u32 ptr, const char* scope) {
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return __builtin_amdgcn_global_load_b128(ptr, scope); //expected-error{{expression is not a string literal}}
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}

‎clang/test/SemaOpenCL/builtins-amdgcn-global-load-store-target-error.cl‎

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// We test loads and stores separately because clang only seems to exit after
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// the first 'target feature' error.
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx9-generic -DTEST_LOAD -S -verify -o - %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx10-1-generic -DTEST_LOAD -S -verify -o - %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx10-3-generic -DTEST_LOAD -S -verify -o - %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx11-generic -DTEST_LOAD -S -verify -o - %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx12-generic -DTEST_LOAD -S -verify -o - %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx9-generic -DTEST_STORE -S -verify -o - %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx10-1-generic -DTEST_STORE -S -verify -o - %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx10-3-generic -DTEST_STORE -S -verify -o - %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx11-generic -DTEST_STORE -S -verify -o - %s
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// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx12-generic -DTEST_STORE -S -verify -o - %s
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// REQUIRES: amdgpu-registered-target
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typedef __attribute__((__vector_size__(4 * sizeof(unsigned int)))) unsigned int v4u32;
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typedef v4u32 __global *global_ptr_to_v4u32;
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#ifdef TEST_LOAD
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v4u32 test_amdgcn_global_load_b128_01(global_ptr_to_v4u32 ptr, const char* scope) {
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return __builtin_amdgcn_global_load_b128(ptr, ""); // expected-error{{'__builtin_amdgcn_global_load_b128' needs target feature gfx940-insts}}
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}
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#endif
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#ifdef TEST_STORE
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void test_amdgcn_global_store_b128_01(global_ptr_to_v4u32 ptr, v4u32 data, const char* scope) {
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__builtin_amdgcn_global_store_b128(ptr, data, ""); // expected-error{{'__builtin_amdgcn_global_store_b128' needs target feature gfx940-insts}}
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}
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#endif

‎llvm/docs/AMDGPUUsage.rst‎

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@@ -1513,6 +1513,86 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
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* 1 - Data cache.
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Instruction cache prefetches are unsafe on invalid address.
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llvm.amdgcn.global.load.b128 This intrinsic is supported on gfx942, gfx950.
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Signature:
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.. code-block:: llvm
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<4 x i32> @llvm.amdgcn.raw.load.store.b128(
1524+
ptr addrspace(1), ; source
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metadata) ; scope - e.g. '!0' where '!0 = !{!"wavegroup"}'
1526+
1527+
Reads the value from the source address with cache behavior
1528+
specified by the scope.
1529+
1530+
For gfc942 and gfx950 devices, this emits a
1531+
``global_load_dwordx4`` instruction with the appropriate
1532+
``SC0`` and ``SC1`` bits set.
1533+
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Valid values for scope are
1535+
1536+
===================== =============================================================
1537+
scope architecture name
1538+
===================== =============================================================
1539+
``"wavefront"`` wave
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``"workgroup"`` group
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``"agent"`` device
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``""`` (empty string) system
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===================== =============================================================
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For semantics on gfx942, see Table 47 in section 9.1.10
1549+
"Memory Scope and Temporal Controls" of the "AMD Instinct
1550+
MI300" Instruction Set Architecture Reference.
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1552+
For semantics on gfx950, see Table 49 in section 9.1.10
1553+
"Memory Scope and Temporal Controls" of the CDNA4
1554+
Instruction Set Architecture Reference.
1555+
1556+
llvm.amdgcn.global.store.b128 This intrinsic is supported on gfx942, gfx950.
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Signature:
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1560+
.. code-block:: llvm
1561+
1562+
void @llvm.amdgcn.global.store.b128(
1563+
ptr addrspace(1), ; destination
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<4 x i32>, ; value
1565+
metadata) ; scope - e.g. '!0' where '!0 = !{!"wavegroup"}'
1566+
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Writes the value to the destination address with cache
1568+
behavior specified by the scope.
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1570+
For gfc942 and gfx950 devices, this emits a
1571+
``global_store_dwordx4`` instruction with the appropriate
1572+
``SC0`` and ``SC1`` bits set.
1573+
1574+
Valid values for scope are
1575+
1576+
===================== =============================================================
1577+
scope architecture name
1578+
===================== =============================================================
1579+
``"wavefront"`` wave
1580+
1581+
``"workgroup"`` group
1582+
1583+
``"agent"`` device
1584+
1585+
``""`` (empty string) system
1586+
===================== =============================================================
1587+
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For semantics on gfx942, see Table 48 in section 9.1.10
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"Memory Scope and Temporal Controls" of the "AMD Instinct
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MI300" Instruction Set Architecture Reference.
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For semantics on gfx950, see Table 50 in section 9.1.10
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"Memory Scope and Temporal Controls" of the CDNA4
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Instruction Set Architecture Reference.
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