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[RISCV] Add Qualcomm uC Xqcilo (Large Offset Load Store) extension (llvm#123881)
This extension adds eight 48 bit load store instructions. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --------- Co-authored-by: Harsh Chandel <[email protected]>
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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@@ -197,6 +197,7 @@
197197
// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension)
198198
// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
199199
// CHECK-NEXT: xqciint 0.2 'Xqciint' (Qualcomm uC Interrupts Extension)
200+
// CHECK-NEXT: xqcilo 0.2 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
200201
// CHECK-NEXT: xqcilsm 0.2 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
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// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
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// CHECK-EMPTY:

‎llvm/docs/RISCVUsage.rst‎

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@@ -450,6 +450,9 @@ The current vendor extensions supported are:
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``experimental-Xqciint``
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LLVM implements `version 0.2 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcilo``
454+
LLVM implements `version 0.2 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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``experimental-Xqcilsm``
454457
LLVM implements `version 0.2 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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‎llvm/docs/ReleaseNotes.md‎

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@@ -294,6 +294,8 @@ Changes to the RISC-V Backend
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqciint` (Interrupts)
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extension.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcilo` (Large Offset Load Store)
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extension.
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* Added ``Sdext`` and ``Sdtrig`` extensions.
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Changes to the WebAssembly Backend

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

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@@ -1036,6 +1036,16 @@ struct RISCVOperand final : public MCParsedAsmOperand {
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VK == RISCVMCExpr::VK_RISCV_None;
10371037
}
10381038

1039+
bool isSImm26() const {
1040+
if (!isImm())
1041+
return false;
1042+
RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
1043+
int64_t Imm;
1044+
bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
1045+
return IsConstantImm && (VK == RISCVMCExpr::VK_RISCV_None) &&
1046+
isInt<26>(fixImmediateForRV32(Imm, isRV64Imm()));
1047+
}
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10391049
/// getStartLoc - Gets location of the first token of this operand
10401050
SMLoc getStartLoc() const override { return StartLoc; }
10411051
/// getEndLoc - Gets location of the last token of this operand
@@ -1676,6 +1686,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
16761686
(1 << 4),
16771687
"immediate must be in the range");
16781688
}
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case Match_InvalidSImm26:
1690+
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 25),
1691+
(1 << 25) - 1);
16791692
case Match_InvalidRlist: {
16801693
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
16811694
return Error(

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -45,6 +45,10 @@ class RISCVDisassembler : public MCDisassembler {
4545
private:
4646
void addSPOperands(MCInst &MI) const;
4747

48+
DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
49+
ArrayRef<uint8_t> Bytes, uint64_t Address,
50+
raw_ostream &CStream) const;
51+
4852
DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
4953
ArrayRef<uint8_t> Bytes, uint64_t Address,
5054
raw_ostream &CStream) const;
@@ -745,6 +749,27 @@ DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
745749
return MCDisassembler::Fail;
746750
}
747751

752+
DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
753+
ArrayRef<uint8_t> Bytes,
754+
uint64_t Address,
755+
raw_ostream &CS) const {
756+
if (Bytes.size() < 6) {
757+
Size = 0;
758+
return MCDisassembler::Fail;
759+
}
760+
Size = 6;
761+
762+
uint64_t Insn = 0;
763+
for (size_t i = Size; i-- != 0;) {
764+
Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
765+
}
766+
TRY_TO_DECODE_FEATURE(
767+
RISCV::FeatureVendorXqcilo, DecoderTableXqcilo48,
768+
"Qualcomm uC Large Offset Load Store custom 48bit opcode table");
769+
770+
return MCDisassembler::Fail;
771+
}
772+
748773
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
749774
ArrayRef<uint8_t> Bytes,
750775
uint64_t Address,
@@ -760,8 +785,7 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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761786
// 48-bit instructions are encoded as 0bxx011111.
762787
if ((Bytes[0] & 0b11'1111) == 0b01'1111) {
763-
Size = Bytes.size() >= 6 ? 6 : 0;
764-
return MCDisassembler::Fail;
788+
return getInstruction48(MI, Size, Bytes, Address, CS);
765789
}
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767791
// 64-bit instructions are encoded as 0x0111111.

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

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@@ -332,6 +332,7 @@ enum OperandType : unsigned {
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OPERAND_SIMM10_LSB0000_NONZERO,
333333
OPERAND_SIMM12,
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OPERAND_SIMM12_LSB00000,
335+
OPERAND_SIMM26,
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OPERAND_CLUI_IMM,
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OPERAND_VTYPEI10,
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OPERAND_VTYPEI11,

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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@@ -1310,6 +1310,14 @@ def HasVendorXqciint
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AssemblerPredicate<(all_of FeatureVendorXqciint),
13111311
"'Xqciint' (Qualcomm uC Interrupts Extension)">;
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1313+
def FeatureVendorXqcilo
1314+
: RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Offset Load Store Extension",
1315+
[FeatureStdExtZca]>;
1316+
def HasVendorXqcilo
1317+
: Predicate<"Subtarget->hasVendorXqcilo()">,
1318+
AssemblerPredicate<(all_of FeatureVendorXqcilo),
1319+
"'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">;
1320+
13131321
//===----------------------------------------------------------------------===//
13141322
// LLVM specific features and extensions
13151323
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp‎

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@@ -2513,6 +2513,7 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI,
25132513
CASE_OPERAND_SIMM(5)
25142514
CASE_OPERAND_SIMM(6)
25152515
CASE_OPERAND_SIMM(12)
2516+
CASE_OPERAND_SIMM(26)
25162517
// clang-format on
25172518
case RISCVOp::OPERAND_SIMM5_PLUS1:
25182519
Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -32,6 +32,8 @@ def uimm10 : RISCVUImmLeafOp<10>;
3232

3333
def uimm11 : RISCVUImmLeafOp<11>;
3434

35+
def simm26 : RISCVSImmLeafOp<26>;
36+
3537
//===----------------------------------------------------------------------===//
3638
// Instruction Formats
3739
//===----------------------------------------------------------------------===//
@@ -198,6 +200,51 @@ class QCIInt_IMM<bits<1> funct1, string opcodestr>
198200
let Inst{24-20} = imm10{9-5};
199201
}
200202

203+
class QCIRVInstEIBase<bits<3> funct3, bits<2> funct2, dag outs,
204+
dag ins, string opcodestr, string argstr>
205+
: RVInst48<outs, ins, opcodestr, argstr, [], InstFormatOther> {
206+
bits<5> rd;
207+
bits<5> rs1;
208+
bits<26> imm;
209+
210+
let Inst{47-32} = imm{25-10};
211+
let Inst{31-30} = funct2;
212+
let Inst{29-20} = imm{9-0};
213+
let Inst{19-15} = rs1;
214+
let Inst{14-12} = funct3;
215+
let Inst{11-7} = rd;
216+
let Inst{6-0} = 0b0011111;
217+
}
218+
219+
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
220+
class QCIRVInstEILoad<bits<3> funct3, bits<2> funct2, string opcodestr>
221+
: QCIRVInstEIBase<funct3, funct2, (outs GPR:$rd),
222+
(ins GPRMem:$rs1, simm26:$imm), opcodestr,
223+
"$rd, ${imm}(${rs1})">;
224+
225+
class QCIRVInstESBase<bits<3> funct3, bits<2> funct2, dag outs,
226+
dag ins, string opcodestr, string argstr>
227+
: RVInst48<outs, ins, opcodestr, argstr, [], InstFormatOther> {
228+
bits<5> rs1;
229+
bits<5> rs2;
230+
bits<26> imm;
231+
232+
let Inst{47-32} = imm{25-10};
233+
let Inst{31-30} = funct2;
234+
let Inst{29-25} = imm{9-5};
235+
let Inst{24-20} = rs2;
236+
let Inst{19-15} = rs1;
237+
let Inst{14-12} = funct3;
238+
let Inst{11-7} = imm{4-0};
239+
let Inst{6-0} = 0b0011111;
240+
}
241+
242+
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
243+
class QCIRVInstESStore<bits<3> funct3, bits<2> funct2, string opcodestr>
244+
: QCIRVInstESBase<funct3, funct2, (outs),
245+
(ins GPRMem:$rs2, GPR:$rs1, simm26:$imm),
246+
opcodestr, "$rs2, ${imm}(${rs1})">;
247+
201248
//===----------------------------------------------------------------------===//
202249
// Instructions
203250
//===----------------------------------------------------------------------===//
@@ -376,6 +423,18 @@ let Predicates = [HasVendorXqciint, IsRV32], DecoderNamespace = "Xqciint" in {
376423
def QC_C_MILEAVERET : QCIRVInst16CI_NONE<0b10100, "qc.c.mileaveret">;
377424
} // Predicates = [HasVendorXqciint, IsRV32], DecoderNamespace = "Xqciint"
378425

426+
let Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo" in {
427+
def QC_E_LB : QCIRVInstEILoad<0b101, 0b00, "qc.e.lb">;
428+
def QC_E_LBU : QCIRVInstEILoad<0b101, 0b01, "qc.e.lbu">;
429+
def QC_E_LH : QCIRVInstEILoad<0b101, 0b10, "qc.e.lh">;
430+
def QC_E_LHU : QCIRVInstEILoad<0b101, 0b11, "qc.e.lhu">;
431+
def QC_E_LW : QCIRVInstEILoad<0b110, 0b00, "qc.e.lw">;
432+
433+
def QC_E_SB : QCIRVInstESStore<0b110, 0b01, "qc.e.sb">;
434+
def QC_E_SH : QCIRVInstESStore<0b110, 0b10, "qc.e.sh">;
435+
def QC_E_SW : QCIRVInstESStore<0b110, 0b11, "qc.e.sw">;
436+
} // Predicates = [HasVendorXqcilo, IsRV32], DecoderNamespace = "Xqcilo"
437+
379438
//===----------------------------------------------------------------------===//
380439
// Aliases
381440
//===----------------------------------------------------------------------===//
@@ -396,3 +455,24 @@ let EmitPriority = 0 in {
396455
(QC_LWMI GPRNoX0:$rd, GPR:$rs1, uimm5nonzero:$length, 0)>;
397456
} // EmitPriority = 0
398457
} // Predicates = [HasVendorXqcilsm, IsRV32]
458+
459+
let Predicates = [HasVendorXqcilo, IsRV32] in {
460+
let EmitPriority = 0 in {
461+
def : InstAlias<"qc.e.lb $rd, (${rs1})",
462+
(QC_E_LB GPR:$rd, GPR:$rs1, 0)>;
463+
def : InstAlias<"qc.e.lbu $rd, (${rs1})",
464+
(QC_E_LBU GPR:$rd, GPR:$rs1, 0)>;
465+
def : InstAlias<"qc.e.lh $rd, (${rs1})",
466+
(QC_E_LH GPR:$rd, GPR:$rs1, 0)>;
467+
def : InstAlias<"qc.e.lhu $rd, (${rs1})",
468+
(QC_E_LHU GPR:$rd, GPR:$rs1, 0)>;
469+
def : InstAlias<"qc.e.lw $rd, (${rs1})",
470+
(QC_E_LW GPR:$rd, GPR:$rs1, 0)>;
471+
def : InstAlias<"qc.e.sb $rs2, (${rs1})",
472+
(QC_E_SB GPR:$rs2, GPR:$rs1, 0)>;
473+
def : InstAlias<"qc.e.sh $rs2, (${rs1})",
474+
(QC_E_SH GPR:$rs2, GPR:$rs1, 0)>;
475+
def : InstAlias<"qc.e.sw $rs2, (${rs1})",
476+
(QC_E_SW GPR:$rs2, GPR:$rs1, 0)>;
477+
} // EmitPriority = 0
478+
} // Predicates = [HasVendorXqcilo, IsRV32]

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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@@ -742,8 +742,8 @@ Error RISCVISAInfo::checkDependency() {
742742
bool HasZvl = MinVLen != 0;
743743
bool HasZcmt = Exts.count("zcmt") != 0;
744744
static constexpr StringLiteral XqciExts[] = {
745-
{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, {"xqcics"},
746-
{"xqcicsr"}, {"xqciint"}, {"xqcilsm"}, {"xqcisls"}};
745+
{"xqcia"}, {"xqciac"}, {"xqcicli"}, {"xqcicm"}, {"xqcics"},
746+
{"xqcicsr"}, {"xqciint"}, {"xqcilo"}, {"xqcilsm"}, {"xqcisls"}};
747747

748748
if (HasI && HasE)
749749
return getIncompatibleError("i", "e");

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