Skip to content

Commit 1fb8a27

Browse files
authored
[NFC][Clang] Fix typo in feature predicate insertion
Due to a botched merge, we currently emit volatile loads from feature predicate globals. These are never foldable, which breaks things. This does not apply to the upstream patch currently under review. Commiting on behalf of github user @AlexVlx
1 parent d3280a4 commit 1fb8a27

File tree

3 files changed

+3
-3
lines changed

3 files changed

+3
-3
lines changed

clang/lib/CodeGen/TargetBuiltins/AMDGPU.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -304,7 +304,7 @@ static Value *GetOrInsertAMDGPUPredicate(CodeGenFunction &CGF, Twine Name) {
304304
P->setExternallyInitialized(true);
305305

306306
return CGF.Builder.CreateLoad(
307-
RawAddress(P, PTy, CharUnits::One(), KnownNonNull), true);
307+
RawAddress(P, PTy, CharUnits::One(), KnownNonNull));
308308
}
309309

310310
Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,

clang/test/CodeGen/amdgpu-builtin-is-invocable.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@
2828
// AMDGCNSPIRV-LABEL: define spir_func void @foo(
2929
// AMDGCNSPIRV-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] {
3030
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
31-
// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load volatile i1, ptr addrspace(1) @llvm.amdgcn.has.gfx10-insts, align 1
31+
// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load i1, ptr addrspace(1) @llvm.amdgcn.has.gfx10-insts, align 1
3232
// AMDGCNSPIRV-NEXT: [[TOBOOL:%.*]] = icmp ne i1 [[TMP0]], false
3333
// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
3434
// AMDGCNSPIRV: [[IF_THEN]]:

clang/test/CodeGen/amdgpu-builtin-processor-is.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@
2626
// AMDGCNSPIRV-LABEL: define spir_func void @foo(
2727
// AMDGCNSPIRV-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] {
2828
// AMDGCNSPIRV-NEXT: [[ENTRY:.*:]]
29-
// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load volatile i1, ptr addrspace(1) @llvm.amdgcn.is.gfx900, align 1
29+
// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load i1, ptr addrspace(1) @llvm.amdgcn.is.gfx900, align 1
3030
// AMDGCNSPIRV-NEXT: [[TOBOOL:%.*]] = icmp ne i1 [[TMP0]], false
3131
// AMDGCNSPIRV-NEXT: br i1 [[TOBOOL]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
3232
// AMDGCNSPIRV: [[IF_THEN]]:

0 commit comments

Comments
 (0)