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[RELAND] AMDGPU: Remove global/flat atomic fadd intrinics (llvm#97051)
These have been replaced with atomicrmw. Change-Id: I0473af680471255679f69852476086f96504e0fd
1 parent 5ef0deb commit 20a9c40

39 files changed

+375
-2222
lines changed

‎clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp‎

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2890,23 +2890,21 @@ CGOpenMPRuntimeGPU::emitFastFPAtomicCall(CodeGenFunction &CGF, LValue X,
28902890
RValue Update, BinaryOperatorKind BO,
28912891
bool IsXBinopExpr) {
28922892
CGBuilderTy &Bld = CGF.Builder;
2893-
unsigned int IID = -1;
2893+
llvm::AtomicRMWInst::BinOp Kind = llvm::AtomicRMWInst::FAdd;
28942894
RValue UpdateFixed = Update;
28952895
switch (BO) {
28962896
case BO_Sub:
28972897
UpdateFixed = RValue::get(Bld.CreateFNeg(Update.getScalarVal()));
2898-
IID = llvm::Intrinsic::amdgcn_flat_atomic_fadd;
2898+
Kind = llvm::AtomicRMWInst::FAdd;
28992899
break;
29002900
case BO_Add:
2901-
IID = llvm::Intrinsic::amdgcn_flat_atomic_fadd;
2901+
Kind = llvm::AtomicRMWInst::FAdd;
29022902
break;
29032903
case BO_LT:
2904-
IID = IsXBinopExpr ? llvm::Intrinsic::amdgcn_flat_atomic_fmax
2905-
: llvm::Intrinsic::amdgcn_flat_atomic_fmin;
2904+
Kind = IsXBinopExpr ? llvm::AtomicRMWInst::FMax : llvm::AtomicRMWInst::FMin;
29062905
break;
29072906
case BO_GT:
2908-
IID = IsXBinopExpr ? llvm::Intrinsic::amdgcn_flat_atomic_fmin
2909-
: llvm::Intrinsic::amdgcn_flat_atomic_fmax;
2907+
Kind = IsXBinopExpr ? llvm::AtomicRMWInst::FMin : llvm::AtomicRMWInst::FMax;
29102908
break;
29112909
default:
29122910
// remaining operations are not supported yet
@@ -2930,10 +2928,9 @@ CGOpenMPRuntimeGPU::emitFastFPAtomicCall(CodeGenFunction &CGF, LValue X,
29302928
CGM.getModule(), OMPRTL___kmpc_unsafeAtomicAdd),
29312929
FPAtomicArgs);
29322930
} else {
2933-
llvm::Function *AtomicF = CGM.getIntrinsic(
2934-
IID, {FPAtomicArgs[1]->getType(), FPAtomicArgs[0]->getType(),
2935-
FPAtomicArgs[1]->getType()});
2936-
CallInst = CGF.EmitNounwindRuntimeCall(AtomicF, FPAtomicArgs);
2931+
CallInst =
2932+
Bld.CreateAtomicRMW(Kind, X.getAddress(), FPAtomicArgs[1],
2933+
llvm::AtomicOrdering::SequentiallyConsistent);
29372934
}
29382935
return std::make_pair(true, RValue::get(CallInst));
29392936
}

‎clang/test/OpenMP/amdgcn_target_fast_fp_apu.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ int main(){
5252
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
5353
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
5454
// CHECK: user_code.entry:
55-
// CHECK-NEXT: [[TMP2:%.*]] = call float @llvm.amdgcn.flat.atomic.fadd.f32.p0.f32(ptr [[TMP0]], float 1.000000e+00) #[[ATTR2:[0-9]+]]
55+
// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw fadd ptr [[TMP0]], float 1.000000e+00 seq_cst, align 4
5656
// CHECK-NEXT: call void @__kmpc_target_deinit()
5757
// CHECK-NEXT: ret void
5858
// CHECK: worker.exit:
@@ -73,7 +73,7 @@ int main(){
7373
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
7474
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
7575
// CHECK: user_code.entry:
76-
// CHECK-NEXT: [[TMP2:%.*]] = call float @llvm.amdgcn.flat.atomic.fadd.f32.p0.f32(ptr [[TMP0]], float 1.000000e+00) #[[ATTR2]]
76+
// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw fadd ptr [[TMP0]], float 1.000000e+00 seq_cst, align 4
7777
// CHECK-NEXT: call void @__kmpc_target_deinit()
7878
// CHECK-NEXT: ret void
7979
// CHECK: worker.exit:
@@ -94,7 +94,7 @@ int main(){
9494
// CHECK-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
9595
// CHECK-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
9696
// CHECK: user_code.entry:
97-
// CHECK-NEXT: [[TMP2:%.*]] = call float @llvm.amdgcn.flat.atomic.fadd.f32.p0.f32(ptr [[TMP0]], float 1.000000e+00) #[[ATTR2]]
97+
// CHECK-NEXT: [[TMP2:%.*]] = atomicrmw fadd ptr [[TMP0]], float 1.000000e+00 seq_cst, align 4
9898
// CHECK-NEXT: call void @__kmpc_target_deinit()
9999
// CHECK-NEXT: ret void
100100
// CHECK: worker.exit:

‎clang/test/OpenMP/amdgcn_usm_atomics_hint.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ double test_amdgcn_target_atomic_hints() {
2626

2727
#pragma omp target teams distribute parallel for map(tofrom:a,b)
2828
for (int i = 0; i < N; i++) {
29-
// CHECK-HINTS: call {{.*}} @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64
29+
// CHECK-HINTS: = atomicrmw fadd
3030
#pragma omp atomic hint(amd_fast_fp_atomics)
3131
a+=(double)i;
3232

@@ -49,11 +49,11 @@ double test_amdgcn_target_atomic_unsafe_opt() {
4949

5050
#pragma omp target teams distribute parallel for map(tofrom:a,b,c)
5151
for (int i = 0; i < N; i++) {
52-
// CHECK-FLAG-UNSAFE: call {{.*}} @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64
52+
// CHECK-FLAG-UNSAFE: = atomicrmw fadd
5353
#pragma omp atomic
5454
a+=(double)i;
5555

56-
// CHECK-FLAG-UNSAFE: call {{.*}} @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64
56+
// CHECK-FLAG-UNSAFE: = atomicrmw fadd
5757
#pragma omp atomic hint(amd_fast_fp_atomics)
5858
b+=(double)i;
5959

‎llvm/docs/ReleaseNotes.rst‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -78,6 +78,11 @@ Changes to the AArch64 Backend
7878
Changes to the AMDGPU Backend
7979
-----------------------------
8080

81+
* Removed ``llvm.amdgcn.flat.atomic.fadd`` and
82+
``llvm.amdgcn.global.atomic.fadd`` intrinsics. Users should use the
83+
:ref:`atomicrmw <i_atomicrmw>` instruction with `fadd` and
84+
addrspace(0) or addrspace(1) instead.
85+
8186
Changes to the ARM Backend
8287
--------------------------
8388

‎llvm/include/llvm/IR/IntrinsicsAMDGPU.td‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3027,8 +3027,6 @@ def int_amdgcn_dot4_f32_bf8_bf8 : AMDGPU8bitFloatDot4Intrinsic;
30273027
// gfx908 intrinsics
30283028
// ===----------------------------------------------------------------------===//
30293029

3030-
def int_amdgcn_global_atomic_fadd : AMDGPUAtomicRtn<llvm_anyfloat_ty>;
3031-
30323030
// llvm.amdgcn.mfma.*.* vdst, srcA, srcB, srcC, cbsz, abid, blgp
30333031
class AMDGPUMfmaIntrinsic<LLVMType DestTy, LLVMType SrcABTy> :
30343032
ClangBuiltin<!subst("int", "__builtin", NAME)>,
@@ -3067,7 +3065,6 @@ def int_amdgcn_mfma_f32_16x16x8bf16 : AMDGPUMfmaIntrinsic<llvm_v4f32_ty, llvm_v
30673065

30683066
def int_amdgcn_global_atomic_fmin : AMDGPUAtomicRtn<llvm_anyfloat_ty>;
30693067
def int_amdgcn_global_atomic_fmax : AMDGPUAtomicRtn<llvm_anyfloat_ty>;
3070-
def int_amdgcn_flat_atomic_fadd : AMDGPUAtomicRtn<llvm_anyfloat_ty>;
30713068
def int_amdgcn_flat_atomic_fmin : AMDGPUAtomicRtn<llvm_anyfloat_ty>;
30723069
def int_amdgcn_flat_atomic_fmax : AMDGPUAtomicRtn<llvm_anyfloat_ty>;
30733070

‎llvm/lib/IR/AutoUpgrade.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1035,8 +1035,8 @@ static bool upgradeIntrinsicFunction1(Function *F, Function *&NewFn,
10351035

10361036
if (Name.starts_with("ds.fadd") || Name.starts_with("ds.fmin") ||
10371037
Name.starts_with("ds.fmax") ||
1038-
Name.starts_with("global.atomic.fadd.v2bf16") ||
1039-
Name.starts_with("flat.atomic.fadd.v2bf16")) {
1038+
Name.starts_with("global.atomic.fadd") ||
1039+
Name.starts_with("flat.atomic.fadd")) {
10401040
// Replaced with atomicrmw fadd/fmin/fmax, so there's no new
10411041
// declaration.
10421042
NewFn = nullptr;

‎llvm/lib/Target/AMDGPU/AMDGPUInstructions.td‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -618,16 +618,11 @@ multiclass local_addr_space_atomic_op {
618618
}
619619
}
620620

621-
defm int_amdgcn_flat_atomic_fadd : noret_op;
622-
defm int_amdgcn_flat_atomic_fadd : flat_addr_space_atomic_op;
623621
defm int_amdgcn_flat_atomic_fmin : noret_op;
624622
defm int_amdgcn_flat_atomic_fmax : noret_op;
625-
defm int_amdgcn_global_atomic_fadd : global_addr_space_atomic_op;
626-
defm int_amdgcn_flat_atomic_fadd : global_addr_space_atomic_op;
627623
defm int_amdgcn_global_atomic_fmin : noret_op;
628624
defm int_amdgcn_global_atomic_fmax : noret_op;
629625
defm int_amdgcn_global_atomic_csub : noret_op;
630-
defm int_amdgcn_flat_atomic_fadd : local_addr_space_atomic_op;
631626
defm int_amdgcn_global_atomic_ordered_add_b64 : noret_op;
632627
defm int_amdgcn_flat_atomic_fmin_num : noret_op;
633628
defm int_amdgcn_flat_atomic_fmax_num : noret_op;

‎llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4914,13 +4914,11 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
49144914
OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
49154915
break;
49164916
}
4917-
case Intrinsic::amdgcn_global_atomic_fadd:
49184917
case Intrinsic::amdgcn_global_atomic_csub:
49194918
case Intrinsic::amdgcn_global_atomic_fmin:
49204919
case Intrinsic::amdgcn_global_atomic_fmax:
49214920
case Intrinsic::amdgcn_global_atomic_fmin_num:
49224921
case Intrinsic::amdgcn_global_atomic_fmax_num:
4923-
case Intrinsic::amdgcn_flat_atomic_fadd:
49244922
case Intrinsic::amdgcn_flat_atomic_fmin:
49254923
case Intrinsic::amdgcn_flat_atomic_fmax:
49264924
case Intrinsic::amdgcn_flat_atomic_fmin_num:

‎llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -239,13 +239,11 @@ def : SourceOfDivergence<int_r600_read_tidig_y>;
239239
def : SourceOfDivergence<int_r600_read_tidig_z>;
240240
def : SourceOfDivergence<int_amdgcn_atomic_cond_sub_u32>;
241241
def : SourceOfDivergence<int_amdgcn_global_atomic_csub>;
242-
def : SourceOfDivergence<int_amdgcn_global_atomic_fadd>;
243242
def : SourceOfDivergence<int_amdgcn_global_atomic_fmin>;
244243
def : SourceOfDivergence<int_amdgcn_global_atomic_fmax>;
245244
def : SourceOfDivergence<int_amdgcn_global_atomic_fmin_num>;
246245
def : SourceOfDivergence<int_amdgcn_global_atomic_fmax_num>;
247246
def : SourceOfDivergence<int_amdgcn_global_atomic_ordered_add_b64>;
248-
def : SourceOfDivergence<int_amdgcn_flat_atomic_fadd>;
249247
def : SourceOfDivergence<int_amdgcn_flat_atomic_fmin>;
250248
def : SourceOfDivergence<int_amdgcn_flat_atomic_fmax>;
251249
def : SourceOfDivergence<int_amdgcn_flat_atomic_fmin_num>;

‎llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1045,7 +1045,6 @@ bool GCNTTIImpl::collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
10451045
switch (IID) {
10461046
case Intrinsic::amdgcn_is_shared:
10471047
case Intrinsic::amdgcn_is_private:
1048-
case Intrinsic::amdgcn_flat_atomic_fadd:
10491048
case Intrinsic::amdgcn_flat_atomic_fmax:
10501049
case Intrinsic::amdgcn_flat_atomic_fmin:
10511050
case Intrinsic::amdgcn_flat_atomic_fmax_num:
@@ -1107,7 +1106,6 @@ Value *GCNTTIImpl::rewriteIntrinsicWithAddressSpace(IntrinsicInst *II,
11071106
return B.CreateIntrinsic(Intrinsic::ptrmask, {NewV->getType(), MaskTy},
11081107
{NewV, MaskOp});
11091108
}
1110-
case Intrinsic::amdgcn_flat_atomic_fadd:
11111109
case Intrinsic::amdgcn_flat_atomic_fmax:
11121110
case Intrinsic::amdgcn_flat_atomic_fmin:
11131111
case Intrinsic::amdgcn_flat_atomic_fmax_num:

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