merge amd-debug into amd-staging (llvm#1987)

ronlieb · web-flow · commit 25e12af8645f · 2025-05-05T22:17:36.000-04:00
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -614,6 +614,8 @@ class LLVM_ABI MachineFunction {
   void substituteDebugValuesForInst(const MachineInstr &Old, MachineInstr &New,
                                     unsigned MaxOperand = UINT_MAX);
 
+  using SalvageCopySSAResult = std::pair<DebugInstrOperandPair, MachineInstr *>;
+
   /// Find the underlying  defining instruction / operand for a COPY instruction
   /// while in SSA form. Copies do not actually define values -- they move them
   /// between registers. Labelling a COPY-like instruction with an instruction
@@ -625,11 +627,11 @@ class LLVM_ABI MachineFunction {
   /// \p MI The copy-like instruction to salvage.
   /// \p DbgPHICache A container to cache already-solved COPYs.
   /// \returns An instruction/operand pair identifying the defining value.
-  DebugInstrOperandPair
+  SalvageCopySSAResult
   salvageCopySSA(MachineInstr &MI,
-                 DenseMap<Register, DebugInstrOperandPair> &DbgPHICache);
+                 DenseMap<Register, SalvageCopySSAResult> &DbgPHICache);
 
-  DebugInstrOperandPair salvageCopySSAImpl(MachineInstr &MI);
+  SalvageCopySSAResult salvageCopySSAImpl(MachineInstr &MI);
 
   /// Finalise any partially emitted debug instructions. These are DBG_INSTR_REF
   /// instructions where we only knew the vreg of the value they use, not the
diff --git a/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp b/llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
@@ -1195,7 +1195,27 @@ std::optional<NewOpResult> DwarfExpression::traverse(DIOp::Select Select,
 
 std::optional<NewOpResult> DwarfExpression::traverse(DIOp::Composite Composite,
                                                      ChildrenT Children) {
-  return std::nullopt;
+  if (IsFragment)
+    emitOp(dwarf::DW_OP_lit0);
+
+  for (auto &Child : Children) {
+    auto R = traverse(Child.get(), std::nullopt);
+    if (!R)
+      return std::nullopt;
+    TypeSize Size = R->Ty->getPrimitiveSizeInBits();
+    if (!Size.isFixed() || Size.getFixedValue() % 8 != 0)
+      return std::nullopt;
+    emitOp(dwarf::DW_OP_piece);
+    emitUnsigned(Size.getFixedValue() / 8);
+  }
+  emitUserOp(dwarf::DW_OP_LLVM_USER_piece_end);
+
+  if (IsFragment) {
+    emitOp(dwarf::DW_OP_swap);
+    emitOp(dwarf::DW_OP_drop);
+  }
+
+  return NewOpResult{Composite.getResultType(), ValueKind::LocationDesc};
 }
 
 std::optional<NewOpResult> DwarfExpression::traverseMathOp(uint8_t DwarfOp,
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -45,6 +45,7 @@
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/Constant.h"
 #include "llvm/IR/DataLayout.h"
+#include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/EHPersonalities.h"
 #include "llvm/IR/Function.h"
@@ -1052,8 +1053,8 @@ void MachineFunction::substituteDebugValuesForInst(const MachineInstr &Old,
 }
 
 auto MachineFunction::salvageCopySSA(
-    MachineInstr &MI, DenseMap<Register, DebugInstrOperandPair> &DbgPHICache)
-    -> DebugInstrOperandPair {
+    MachineInstr &MI, DenseMap<Register, SalvageCopySSAResult> &DbgPHICache)
+    -> SalvageCopySSAResult {
   const TargetInstrInfo &TII = *getSubtarget().getInstrInfo();
 
   // Check whether this copy-like instruction has already been salvaged into
@@ -1077,7 +1078,7 @@ auto MachineFunction::salvageCopySSA(
 }
 
 auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
-    -> DebugInstrOperandPair {
+    -> SalvageCopySSAResult {
   MachineRegisterInfo &MRI = getRegInfo();
   const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
   const TargetInstrInfo &TII = *getSubtarget().getInstrInfo();
@@ -1175,7 +1176,8 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
     for (auto &MO : Inst->all_defs()) {
       if (MO.getReg() != State.first)
         continue;
-      return ApplySubregisters({Inst->getDebugInstrNum(), MO.getOperandNo()});
+      return {ApplySubregisters({Inst->getDebugInstrNum(), MO.getOperandNo()}),
+              Inst};
     }
 
     llvm_unreachable("Vreg def with no corresponding operand?");
@@ -1195,8 +1197,9 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
       if (!TRI.regsOverlap(RegToSeek, MO.getReg()))
         continue;
 
-      return ApplySubregisters(
-          {ToExamine.getDebugInstrNum(), MO.getOperandNo()});
+      return {
+          ApplySubregisters({ToExamine.getDebugInstrNum(), MO.getOperandNo()}),
+          &ToExamine};
     }
   }
 
@@ -1217,7 +1220,131 @@ auto MachineFunction::salvageCopySSAImpl(MachineInstr &MI)
   Builder.addReg(State.first);
   unsigned NewNum = getNewDebugInstrNum();
   Builder.addImm(NewNum);
-  return ApplySubregisters({NewNum, 0u});
+  return {ApplySubregisters({NewNum, 0u}), nullptr};
+}
+
+/// The Op operand to the DBG_INSTR_REF instruction DbgInstr is a virtual
+/// register defined by the REG_SEQUENCE instruction RegSeq. In order to
+/// finalize DbgInstr to use instruction references, find the defining
+/// instruction for each register in the sequence and compose them with a
+/// DIOpComposite.
+static bool finalizeInstrRefRegSequenceNew(
+    MachineInstr &DbgInstr, MachineOperand &Op, MachineInstr &RegSeq,
+    DenseMap<Register, MachineFunction::SalvageCopySSAResult> &DbgPHICache) {
+
+  const DIExpression *Expr = DbgInstr.getDebugExpression();
+  if (Expr->holdsOldElements())
+    return false;
+
+  auto &MF = *DbgInstr.getParent()->getParent();
+  auto &Ctx = Expr->getContext();
+  auto &TRI = *MF.getSubtarget().getRegisterInfo();
+  auto &TII = *MF.getSubtarget().getInstrInfo();
+  auto &DL = MF.getDataLayout();
+
+  struct Part {
+    MachineFunction::DebugInstrOperandPair DbgInstrNum;
+    unsigned Size;
+    unsigned Offset;
+  };
+  SmallVector<Part> Parts;
+
+  // Walk through the reg sequence, collecting debug-instr-numbers and
+  // subregister piece sizes and offsets into Parts.
+  for (unsigned I = 1; I < RegSeq.getNumOperands(); I += 2) {
+    Register RegOp = RegSeq.getOperand(I).getReg();
+    if (!RegOp.isVirtual())
+      return false;
+
+    unsigned SubReg = RegSeq.getOperand(I + 1).getImm();
+    unsigned SubSize = TRI.getSubRegIdxSize(SubReg);
+    unsigned SubOffset = TRI.getSubRegIdxOffset(SubReg);
+    MachineInstr &DefMI = *MF.getRegInfo().def_instr_begin(RegOp);
+
+    if (DefMI.isCopyLike() || TII.isCopyInstr(DefMI)) {
+      auto P = MF.salvageCopySSA(DefMI, DbgPHICache);
+      Parts.push_back({P.first, SubSize, SubOffset});
+      continue;
+    }
+
+    // Otherwise, identify the operand number that the VReg refers to.
+    unsigned OperandIdx = 0;
+    for (const auto &DefMO : DefMI.operands()) {
+      if (DefMO.isReg() && DefMO.isDef() && DefMO.getReg() == RegOp)
+        break;
+      ++OperandIdx;
+    }
+    assert(OperandIdx < DefMI.getNumOperands());
+
+    // Morph this instr ref to point at the given instruction and operand.
+    unsigned ID = DefMI.getDebugInstrNum();
+    MachineFunction::DebugInstrOperandPair P{ID, OperandIdx};
+    Parts.push_back({P, SubSize, SubOffset});
+  }
+
+  // Line up the Parts and make sure there aren't any gaps, DIOpComposite can't
+  // handle that easily.
+  std::sort(Parts.begin(), Parts.end(),
+            [](auto &LHS, auto &RHS) { return LHS.Offset < RHS.Offset; });
+  for (unsigned I = 1, E = Parts.size(); I < E; ++I)
+    if (Parts[I - 1].Offset + Parts[I - 1].Size != Parts[I].Offset)
+      return false;
+  if (Parts.empty() || Parts[0].Offset)
+    return false;
+
+  unsigned ArgNoToReplace = 0;
+  unsigned NumArgs = DbgInstr.getNumDebugOperands();
+  assert(NumArgs == Expr->getNewNumLocationOperands());
+  for (; ArgNoToReplace != NumArgs; ++ArgNoToReplace)
+    if (&DbgInstr.getDebugOperand(ArgNoToReplace) == &Op)
+      break;
+  if (ArgNoToReplace == NumArgs)
+    return false;
+
+  auto Elems = Expr->getNewElementsRef();
+  auto NewSize = TypeSize::getFixed(Parts.back().Offset + Parts.back().Size);
+  for (DIOp::Variant Elem : *Elems) {
+    // Only replace the argument with a composite if it has the same size as the
+    // parts.
+    if (auto *Arg = std::get_if<DIOp::Arg>(&Elem))
+      if (Arg->getIndex() == ArgNoToReplace &&
+          DL.getTypeSizeInBits(Arg->getResultType()) != NewSize)
+        return false;
+  }
+
+  Op.ChangeToDbgInstrRef(Parts[0].DbgInstrNum.first,
+                         Parts[0].DbgInstrNum.second);
+  if (Parts.size() == 1)
+    return true;
+
+  // Split up the DIOpArg using a DIOpComposite.
+  DIExprBuilder B{Ctx};
+  for (DIOp::Variant Elem : *Elems) {
+    auto *Arg = std::get_if<DIOp::Arg>(&Elem);
+    if (!Arg || Arg->getIndex() != ArgNoToReplace) {
+      B.append(Elem);
+      continue;
+    }
+    bool FirstPart = true;
+    for (const Part &P : Parts) {
+      // Since these arguments have to line up with the order of the operands on
+      // the DBG_INSTR_REF, recycle Arg's index first, it lines up with the Op
+      // that was ChangeToDbgInstrRef'd above.
+      unsigned ArgNo = FirstPart ? Arg->getIndex() : NumArgs++;
+      FirstPart = false;
+      B.append<DIOp::Arg>(ArgNo, IntegerType::get(Ctx, P.Size));
+    }
+    B.append<DIOp::Composite>(Parts.size(), Arg->getResultType());
+  }
+
+  auto *NewExpr = B.intoExpression();
+  for (const Part &P : drop_begin(Parts, 1))
+    DbgInstr.addOperand(MachineOperand::CreateDbgInstrRef(
+        P.DbgInstrNum.first, P.DbgInstrNum.second));
+  DbgInstr.getDebugExpressionOp() = MachineOperand::CreateMetadata(NewExpr);
+  assert(NewExpr->getNewNumLocationOperands() ==
+         DbgInstr.getNumDebugOperands());
+  return true;
 }
 
 void MachineFunction::finalizeDebugInstrRefs() {
@@ -1229,15 +1356,16 @@ void MachineFunction::finalizeDebugInstrRefs() {
     MI.setDebugValueUndef();
   };
 
-  DenseMap<Register, DebugInstrOperandPair> ArgDbgPHIs;
+  DenseMap<Register, SalvageCopySSAResult> ArgDbgPHIs;
   for (auto &MBB : *this) {
     for (auto &MI : MBB) {
       if (!MI.isDebugRef())
         continue;
 
       bool IsValidRef = true;
 
-      for (MachineOperand &MO : MI.debug_operands()) {
+      for (unsigned I = 0; I < MI.getNumDebugOperands(); ++I) {
+        MachineOperand &MO = MI.getDebugOperand(I);
         if (!MO.isReg())
           continue;
 
@@ -1259,7 +1387,12 @@ void MachineFunction::finalizeDebugInstrRefs() {
         // for why this is important.
         if (DefMI.isCopyLike() || TII->isCopyInstr(DefMI)) {
           auto Result = salvageCopySSA(DefMI, ArgDbgPHIs);
-          MO.ChangeToDbgInstrRef(Result.first, Result.second);
+          if (!Result.second || !Result.second->isRegSequence() ||
+              !finalizeInstrRefRegSequenceNew(MI, MO, *Result.second,
+                                              ArgDbgPHIs))
+            MO.ChangeToDbgInstrRef(Result.first.first, Result.first.second);
+        } else if (DefMI.isRegSequence() &&
+                   finalizeInstrRefRegSequenceNew(MI, MO, DefMI, ArgDbgPHIs)) {
         } else {
           // Otherwise, identify the operand number that the VReg refers to.
           unsigned OperandIdx = 0;
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -882,7 +882,8 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
     // Avoid copy like instructions: they don't define values, only move them.
     // Leave a virtual-register reference until it can be fixed up later, to
     // find the underlying value definition.
-    if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI)) {
+    if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI) ||
+        (Expr->holdsNewElements() && DefMI->isRegSequence())) {
       AddVRegOp(VReg);
       continue;
     }
diff --git a/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp b/llvm/lib/Target/AMDGPU/SIInsertHardClauses.cpp
@@ -167,18 +167,61 @@ class SIInsertHardClauses {
     SmallVector<const MachineOperand *, 4> BaseOps;
   };
 
+  void substituteDebugInstrNumbersToBundleHeader(MachineInstr &FirstInBundle) {
+    auto *MBB = FirstInBundle.getParent();
+    auto *MF = MBB->getParent();
+
+    // Make a map from registers defined within the bundle to their defining
+    // debug instruction number and operand.
+    DenseMap<Register, std::pair<unsigned, unsigned>> RegDefs;
+    for (const MachineOperand &Op : const_mi_bundle_ops(FirstInBundle)) {
+      const MachineInstr &MI = *Op.getParent();
+      if (!MI.isBundle() && Op.isReg() && Op.isDef())
+        RegDefs[Op.getReg()] = {MI.peekDebugInstrNum(), Op.getOperandNo()};
+    }
+
+    MachineInstr &BundleHeader = *std::prev(FirstInBundle.getIterator());
+    for (const MachineOperand &HeaderOp : BundleHeader.operands()) {
+      if (!HeaderOp.isReg() || !HeaderOp.isDef() || HeaderOp.isDead())
+        continue;
+      auto It = RegDefs.find(HeaderOp.getReg());
+      if (It == RegDefs.end())
+        continue;
+      auto [DINum, OpNum] = It->second;
+      if (DINum == 0)
+        continue;
+      MF->makeDebugValueSubstitution(
+          {DINum, OpNum},
+          {BundleHeader.getDebugInstrNum(), HeaderOp.getOperandNo()});
+    }
+  }
+
   bool emitClause(const ClauseInfo &CI, const SIInstrInfo *SII) {
     if (CI.First == CI.Last)
       return false;
     assert(CI.Length <= ST->maxHardClauseLength() &&
            "Hard clause is too long!");
 
     auto &MBB = *CI.First->getParent();
+    bool NeedDebugSubs = false;
+    // Move debug instructions before the bundle and check if debug
+    // substitutions need to be added to the bundle header.
+    for (auto It = CI.First->getIterator(),
+              E = std::next(CI.Last->getIterator());
+         It != E;) {
+      auto MI = It++;
+      if (MI->isDebugInstr())
+        MBB.splice(CI.First, &MBB, MI);
+      else if (MI->peekDebugInstrNum() != 0)
+        NeedDebugSubs = true;
+    }
     auto ClauseMI =
         BuildMI(MBB, *CI.First, DebugLoc(), SII->get(AMDGPU::S_CLAUSE))
             .addImm(CI.Length - 1);
     finalizeBundle(MBB, ClauseMI->getIterator(),
                    std::next(CI.Last->getIterator()));
+    if (NeedDebugSubs)
+      substituteDebugInstrNumbersToBundleHeader(*ClauseMI);
     return true;
   }
 
diff --git a/llvm/test/DebugInfo/AMDGPU/hard-clauses.mir b/llvm/test/DebugInfo/AMDGPU/hard-clauses.mir
@@ -0,0 +1,57 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s
+
+# CHECK-LABEL: name: debug_instrs
+# CHECK-LABEL: debugValueSubstitutions:
+# CHECK-NEXT: - { srcinst: 3, srcop: 0, dstinst: 4, dstop: 0, subreg: 0 }
+# CHECK-NEXT: - { srcinst: 2, srcop: 0, dstinst: 4, dstop: 3, subreg: 0 }
+
+---
+name: debug_instrs
+tracksRegLiveness: true
+debugInstrRef: true
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: DBG_VALUE_LIST
+    ; CHECK-NEXT: DBG_PHI
+    ; CHECK-NEXT: DBG_INSTR_REF
+    ; CHECK-NEXT: BUNDLE implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit $sgpr0_sgpr1, debug-instr-number 4 {
+    ; CHECK-NEXT:   S_CLAUSE 2
+    ; CHECK-NEXT:   $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, debug-instr-number 1
+    ; CHECK-NEXT:   $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0, debug-instr-number 2
+    ; CHECK-NEXT:   $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 3
+    ; CHECK-NEXT: }
+    ; CHECK-NEXT: DBG_VALUE
+    DBG_VALUE_LIST
+    $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, debug-instr-number 1
+    DBG_PHI
+    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0, debug-instr-number 2
+    DBG_INSTR_REF
+    $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 3
+    DBG_VALUE
+...
+
+# CHECK-LABEL: name: only_last_instr
+# CHECK-LABEL: debugValueSubstitutions:
+# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 3, subreg: 0 }
+
+---
+name: only_last_instr
+tracksRegLiveness: true
+debugInstrRef: true
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+    ; CHECK: liveins: $sgpr0_sgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: BUNDLE implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit $sgpr0_sgpr1, debug-instr-number 2 {
+    ; CHECK-NEXT:   S_CLAUSE 1
+    ; CHECK-NEXT:   $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0
+    ; CHECK-NEXT:   $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 1
+    ; CHECK-NEXT: }
+    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0
+    $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 8, 0, debug-instr-number 1
+...
diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-subregs.mir b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-diop-diexpression-subregs.mir
diff --git a/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-instruction-bundle.ll b/llvm/test/DebugInfo/AMDGPU/heterogeneous-dwarf-instruction-bundle.ll
diff --git a/llvm/test/DebugInfo/AMDGPU/reg-sequence-salvage.ll b/llvm/test/DebugInfo/AMDGPU/reg-sequence-salvage.ll
