Revert "[AMDGPU] Split VGPR regalloc pipeline"

This reverts commit 6387cf2.

Change-Id: Id66615ae86ce2ae900c84dbdbb4932a609d1a1e0

Author: kzhuravl

llvm/include/llvm/CodeGen/MachineRegisterInfo.h

@@ -184,8 +184,6 @@ class MachineRegisterInfo {
       TheDelegate->MRI_NoteCloneVirtualRegister(NewReg, SrcReg);
   }
 
-  const MachineFunction &getMF() const { return *MF; }
-
   //===--------------------------------------------------------------------===//
   // Function State
   //===--------------------------------------------------------------------===//

llvm/lib/Target/AMDGPU/AMDGPU.h

@@ -56,7 +56,6 @@ ModulePass *createAMDGPURemoveIncompatibleFunctionsPass(const TargetMachine *);
 FunctionPass *createAMDGPUCodeGenPreparePass();
 FunctionPass *createAMDGPULateCodeGenPreparePass();
 FunctionPass *createAMDGPUMachineCFGStructurizerPass();
-FunctionPass *createAMDGPUReserveWWMRegsPass();
 FunctionPass *createAMDGPURewriteOutArgumentsPass();
 ModulePass *
 createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
@@ -137,9 +136,6 @@ struct AMDGPULowerModuleLDSPass : PassInfoMixin<AMDGPULowerModuleLDSPass> {
   PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM);
 };
 
-void initializeAMDGPUReserveWWMRegsPass(PassRegistry &);
-extern char &AMDGPUReserveWWMRegsID;
-
 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
 extern char &AMDGPURewriteOutArgumentsID;
 

llvm/lib/Target/AMDGPU/AMDGPUReserveWWMRegs.cpp

@@ -81,12 +81,6 @@ class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
     : RegisterRegAllocBase(N, D, C) {}
 };
 
-class WWMRegisterRegAlloc : public RegisterRegAllocBase<WWMRegisterRegAlloc> {
-public:
-  WWMRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
-      : RegisterRegAllocBase(N, D, C) {}
-};
-
 static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
                               const MachineRegisterInfo &MRI,
                               const Register Reg) {
@@ -101,24 +95,13 @@ static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
   return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(RC);
 }
 
-static bool onlyAllocateWWMRegs(const TargetRegisterInfo &TRI,
-                                const MachineRegisterInfo &MRI,
-                                const Register Reg) {
-  const SIMachineFunctionInfo *MFI =
-      MRI.getMF().getInfo<SIMachineFunctionInfo>();
-  const TargetRegisterClass *RC = MRI.getRegClass(Reg);
-  return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(RC) &&
-         MFI->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG);
-}
-
-/// -{sgpr|wwm|vgpr}-regalloc=... command line option.
+/// -{sgpr|vgpr}-regalloc=... command line option.
 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
 
 /// A dummy default pass factory indicates whether the register allocator is
 /// overridden on the command line.
 static llvm::once_flag InitializeDefaultSGPRRegisterAllocatorFlag;
 static llvm::once_flag InitializeDefaultVGPRRegisterAllocatorFlag;
-static llvm::once_flag InitializeDefaultWWMRegisterAllocatorFlag;
 
 static SGPRRegisterRegAlloc
 defaultSGPRRegAlloc("default",
@@ -135,11 +118,6 @@ static cl::opt<VGPRRegisterRegAlloc::FunctionPassCtor, false,
 VGPRRegAlloc("vgpr-regalloc", cl::Hidden, cl::init(&useDefaultRegisterAllocator),
              cl::desc("Register allocator to use for VGPRs"));
 
-static cl::opt<WWMRegisterRegAlloc::FunctionPassCtor, false,
-               RegisterPassParser<WWMRegisterRegAlloc>>
-    WWMRegAlloc("wwm-regalloc", cl::Hidden,
-                cl::init(&useDefaultRegisterAllocator),
-                cl::desc("Register allocator to use for WWM registers"));
 
 static void initializeDefaultSGPRRegisterAllocatorOnce() {
   RegisterRegAlloc::FunctionPassCtor Ctor = SGPRRegisterRegAlloc::getDefault();
@@ -159,15 +137,6 @@ static void initializeDefaultVGPRRegisterAllocatorOnce() {
   }
 }
 
-static void initializeDefaultWWMRegisterAllocatorOnce() {
-  RegisterRegAlloc::FunctionPassCtor Ctor = WWMRegisterRegAlloc::getDefault();
-
-  if (!Ctor) {
-    Ctor = WWMRegAlloc;
-    WWMRegisterRegAlloc::setDefault(WWMRegAlloc);
-  }
-}
-
 static FunctionPass *createBasicSGPRRegisterAllocator() {
   return createBasicRegisterAllocator(onlyAllocateSGPRs);
 }
@@ -192,18 +161,6 @@ static FunctionPass *createFastVGPRRegisterAllocator() {
   return createFastRegisterAllocator(onlyAllocateVGPRs, true);
 }
 
-static FunctionPass *createBasicWWMRegisterAllocator() {
-  return createBasicRegisterAllocator(onlyAllocateWWMRegs);
-}
-
-static FunctionPass *createGreedyWWMRegisterAllocator() {
-  return createGreedyRegisterAllocator(onlyAllocateWWMRegs);
-}
-
-static FunctionPass *createFastWWMRegisterAllocator() {
-  return createFastRegisterAllocator(onlyAllocateWWMRegs, false);
-}
-
 static SGPRRegisterRegAlloc basicRegAllocSGPR(
   "basic", "basic register allocator", createBasicSGPRRegisterAllocator);
 static SGPRRegisterRegAlloc greedyRegAllocSGPR(
@@ -220,16 +177,7 @@ static VGPRRegisterRegAlloc greedyRegAllocVGPR(
 
 static VGPRRegisterRegAlloc fastRegAllocVGPR(
   "fast", "fast register allocator", createFastVGPRRegisterAllocator);
-
-static WWMRegisterRegAlloc basicRegAllocWWMReg("basic",
-                                               "basic register allocator",
-                                               createBasicWWMRegisterAllocator);
-static WWMRegisterRegAlloc
-    greedyRegAllocWWMReg("greedy", "greedy register allocator",
-                         createGreedyWWMRegisterAllocator);
-static WWMRegisterRegAlloc fastRegAllocWWMReg("fast", "fast register allocator",
-                                              createFastWWMRegisterAllocator);
-} // namespace
+}
 
 static cl::opt<bool>
 EnableEarlyIfConversion("amdgpu-early-ifcvt", cl::Hidden,
@@ -477,7 +425,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
   initializeAMDGPURemoveIncompatibleFunctionsPass(*PR);
   initializeAMDGPUSwLowerLDSLegacyPass(*PR);
   initializeAMDGPULowerModuleLDSLegacyPass(*PR);
-  initializeAMDGPUReserveWWMRegsPass(*PR);
   initializeAMDGPURewriteOutArgumentsPass(*PR);
   initializeAMDGPURewriteUndefForPHILegacyPass(*PR);
   initializeAMDGPUUnifyMetadataPass(*PR);
@@ -1067,7 +1014,6 @@ class GCNPassConfig final : public AMDGPUPassConfig {
 
   FunctionPass *createSGPRAllocPass(bool Optimized);
   FunctionPass *createVGPRAllocPass(bool Optimized);
-  FunctionPass *createWWMRegAllocPass(bool Optimized);
   FunctionPass *createRegAllocPass(bool Optimized) override;
 
   bool addRegAssignAndRewriteFast() override;
@@ -1464,6 +1410,7 @@ void GCNPassConfig::addOptimizedRegAlloc() {
 }
 
 bool GCNPassConfig::addPreRewrite() {
+  addPass(&SILowerWWMCopiesID);
   if (EnableRegReassign)
     addPass(&GCNNSAReassignID);
   return true;
@@ -1499,28 +1446,12 @@ FunctionPass *GCNPassConfig::createVGPRAllocPass(bool Optimized) {
   return createFastVGPRRegisterAllocator();
 }
 
-FunctionPass *GCNPassConfig::createWWMRegAllocPass(bool Optimized) {
-  // Initialize the global default.
-  llvm::call_once(InitializeDefaultWWMRegisterAllocatorFlag,
-                  initializeDefaultWWMRegisterAllocatorOnce);
-
-  RegisterRegAlloc::FunctionPassCtor Ctor = WWMRegisterRegAlloc::getDefault();
-  if (Ctor != useDefaultRegisterAllocator)
-    return Ctor();
-
-  if (Optimized)
-    return createGreedyWWMRegisterAllocator();
-
-  return createFastWWMRegisterAllocator();
-}
-
 FunctionPass *GCNPassConfig::createRegAllocPass(bool Optimized) {
   llvm_unreachable("should not be used");
 }
 
 static const char RegAllocOptNotSupportedMessage[] =
-    "-regalloc not supported with amdgcn. Use -sgpr-regalloc, -wwm-regalloc, "
-    "and -vgpr-regalloc";
+  "-regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc";
 
 bool GCNPassConfig::addRegAssignAndRewriteFast() {
   if (!usingDefaultRegAlloc())
@@ -1532,19 +1463,11 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
 
   // Equivalent of PEI for SGPRs.
   addPass(&SILowerSGPRSpillsID);
-
-  // To Allocate wwm registers used in whole quad mode operations (for shaders).
   addPass(&SIPreAllocateWWMRegsID);
 
-  // For allocating other wwm register operands.
-  addPass(createWWMRegAllocPass(false));
-
-  addPass(&SILowerWWMCopiesID);
-  addPass(&AMDGPUReserveWWMRegsID);
-
-  // For allocating regular VGPRs.
   addPass(createVGPRAllocPass(false));
 
+  addPass(&SILowerWWMCopiesID);
   return true;
 }
 
@@ -1564,17 +1487,8 @@ bool GCNPassConfig::addRegAssignAndRewriteOptimized() {
 
   // Equivalent of PEI for SGPRs.
   addPass(&SILowerSGPRSpillsID);
-
-  // To Allocate wwm registers used in whole quad mode operations (for shaders).
   addPass(&SIPreAllocateWWMRegsID);
 
-  // For allocating other whole wave mode registers.
-  addPass(createWWMRegAllocPass(true));
-  addPass(&SILowerWWMCopiesID);
-  addPass(createVirtRegRewriter(false));
-  addPass(&AMDGPUReserveWWMRegsID);
-
-  // For allocating regular VGPRs.
   addPass(createVGPRAllocPass(true));
 
   addPreRewrite();

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

@@ -95,7 +95,6 @@ add_llvm_target(AMDGPUCodeGen
   AMDGPURegBankSelect.cpp
   AMDGPURegisterBankInfo.cpp
   AMDGPURemoveIncompatibleFunctions.cpp
-  AMDGPUReserveWWMRegs.cpp
   AMDGPUResourceUsageAnalysis.cpp
   AMDGPURewriteOutArguments.cpp
   AMDGPURewriteUndefForPHI.cpp