[RISCV] Add IsRV32 some patterns in RISCVInstrInfoXTHead.td.

topperc · topperc · commit 2bf6751522e8 · 2024-11-19T21:41:14.000-08:00
This restores the code to its original state before I experimented
with making i32 a legal type.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -769,7 +769,9 @@ defm : LdIdxPat<zextloadi16, TH_LRHU>;
 
 defm : StIdxPat<truncstorei8, TH_SRB, GPR>;
 defm : StIdxPat<truncstorei16, TH_SRH, GPR>;
+}
 
+let Predicates = [HasVendorXTHeadMemIdx, IsRV32] in {
 defm : LdIdxPat<load, TH_LRW, i32>;
 defm : StIdxPat<store, TH_SRW, GPR, i32>;
 }

Original file line number	Diff line number	Diff line change
`@@ -769,7 +769,9 @@ defm : LdIdxPat<zextloadi16, TH_LRHU>;`
`769`	`769`
`770`	`770`	`defm : StIdxPat<truncstorei8, TH_SRB, GPR>;`
`771`	`771`	`defm : StIdxPat<truncstorei16, TH_SRH, GPR>;`
	`772`	`+}`
`772`	`773`
	`774`	`+let Predicates = [HasVendorXTHeadMemIdx, IsRV32] in {`
`773`	`775`	`defm : LdIdxPat<load, TH_LRW, i32>;`
`774`	`776`	`defm : StIdxPat<store, TH_SRW, GPR, i32>;`
`775`	`777`	`}`