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[LV] Add early-exit tests with VF=1 IC=2.
Adds tests for llvm#154967 to check early-exit vectorization with interleaving only.
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‎llvm/test/Transforms/LoopVectorize/single-early-exit-interleave-only.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
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; RUN: opt -p loop-vectorize -force-vector-width=1 -force-vector-interleave=2 -S %s | FileCheck %s
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; FIXME: currently the live-outs are not handled correctly.
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; Test for https://github.com/llvm/llvm-project/issues/154967.
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define i8 @iv_used_in_exit_with_math(i8 noundef %g) {
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; CHECK-LABEL: define i8 @iv_used_in_exit_with_math(
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; CHECK-SAME: i8 noundef [[G:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX]] to i8
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; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[OFFSET_IDX]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i8 1, [[OFFSET_IDX]]
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; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i8 1, [[TMP0]]
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; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP1]], [[G]]
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; CHECK-NEXT: [[TMP4:%.*]] = and i8 [[TMP2]], [[G]]
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i8 [[TMP3]], 0
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i8 [[TMP4]], 0
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
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; CHECK-NEXT: [[TMP7:%.*]] = xor i1 [[TMP5]], true
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; CHECK-NEXT: [[TMP8:%.*]] = xor i1 [[TMP6]], true
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; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]]
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; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], 4
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; CHECK-NEXT: [[TMP11:%.*]] = or i1 [[TMP9]], [[TMP10]]
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; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_SPLIT]]:
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; CHECK-NEXT: br i1 [[TMP9]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[RETURN:.*]]
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; CHECK: [[VECTOR_EARLY_EXIT]]:
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; CHECK-NEXT: br label %[[RETURN]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
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; CHECK: [[LOOP_HEADER]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i8 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; CHECK-NEXT: [[S:%.*]] = shl nuw i8 1, [[IV]]
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; CHECK-NEXT: [[A:%.*]] = and i8 [[S]], [[G]]
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; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[A]], 0
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; CHECK-NEXT: br i1 [[C]], label %[[LOOP_LATCH]], label %[[RETURN]]
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; CHECK: [[LOOP_LATCH]]:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i8 [[IV]], 1
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i8 [[IV_NEXT]], 4
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; CHECK-NEXT: br i1 [[EC]], label %[[RETURN]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[RETURN]]:
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; CHECK-NEXT: [[RES_IV1:%.*]] = phi i8 [ 32, %[[LOOP_LATCH]] ], [ [[IV]], %[[LOOP_HEADER]] ], [ 32, %[[MIDDLE_BLOCK]] ], [ [[OFFSET_IDX]], %[[VECTOR_EARLY_EXIT]] ]
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; CHECK-NEXT: [[RES_IV2:%.*]] = phi i8 [ 0, %[[LOOP_LATCH]] ], [ [[IV]], %[[LOOP_HEADER]] ], [ 0, %[[MIDDLE_BLOCK]] ], [ [[OFFSET_IDX]], %[[VECTOR_EARLY_EXIT]] ]
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; CHECK-NEXT: [[RES:%.*]] = add i8 [[RES_IV1]], [[RES_IV2]]
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; CHECK-NEXT: ret i8 [[RES]]
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;
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i8 [ 0, %entry ], [ %iv.next, %loop.latch ]
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%s = shl nuw i8 1, %iv
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%a = and i8 %s, %g
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%c = icmp eq i8 %a, 0
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br i1 %c, label %loop.latch, label %return
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loop.latch:
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%iv.next = add nuw nsw i8 %iv, 1
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%ec = icmp eq i8 %iv.next, 4
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br i1 %ec, label %return, label %loop.header
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return:
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%res.iv1 = phi i8 [ 32, %loop.latch ], [ %iv, %loop.header ]
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%res.iv2 = phi i8 [ 0, %loop.latch ], [ %iv, %loop.header ]
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%res = add i8 %res.iv1, %res.iv2
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ret i8 %res
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}
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define i32 @iv_used_in_exit_with_loads(ptr align 4 dereferenceable(128) %src) {
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; CHECK-LABEL: define i32 @iv_used_in_exit_with_loads(
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; CHECK-SAME: ptr align 4 dereferenceable(128) [[SRC:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i32 [[INDEX]]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i32 [[TMP0]]
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; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP1]], align 4
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP2]], align 4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP3]], 0
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[TMP4]], 0
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
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; CHECK-NEXT: [[TMP7:%.*]] = xor i1 [[TMP5]], true
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; CHECK-NEXT: [[TMP8:%.*]] = xor i1 [[TMP6]], true
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; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]]
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; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], 32
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; CHECK-NEXT: [[TMP11:%.*]] = or i1 [[TMP9]], [[TMP10]]
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; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_SPLIT:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: [[MIDDLE_SPLIT]]:
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; CHECK-NEXT: br i1 [[TMP9]], label %[[VECTOR_EARLY_EXIT:.*]], label %[[MIDDLE_BLOCK:.*]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[RETURN:.*]]
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; CHECK: [[VECTOR_EARLY_EXIT]]:
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; CHECK-NEXT: br label %[[RETURN]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: br label %[[LOOP_HEADER:.*]]
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; CHECK: [[LOOP_HEADER]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i32 [[IV]]
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; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP]], align 4
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; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[L]], 0
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; CHECK-NEXT: br i1 [[C]], label %[[LOOP_LATCH]], label %[[RETURN]]
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; CHECK: [[LOOP_LATCH]]:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 32
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; CHECK-NEXT: br i1 [[EC]], label %[[RETURN]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]
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; CHECK: [[RETURN]]:
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; CHECK-NEXT: [[RES_IV1:%.*]] = phi i32 [ 32, %[[LOOP_LATCH]] ], [ [[IV]], %[[LOOP_HEADER]] ], [ 32, %[[MIDDLE_BLOCK]] ], [ [[INDEX]], %[[VECTOR_EARLY_EXIT]] ]
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; CHECK-NEXT: [[RES_IV2:%.*]] = phi i32 [ 0, %[[LOOP_LATCH]] ], [ [[IV]], %[[LOOP_HEADER]] ], [ 0, %[[MIDDLE_BLOCK]] ], [ [[INDEX]], %[[VECTOR_EARLY_EXIT]] ]
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; CHECK-NEXT: [[RES:%.*]] = add i32 [[RES_IV1]], [[RES_IV2]]
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; CHECK-NEXT: ret i32 [[RES]]
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;
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entry:
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br label %loop.header
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loop.header:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ]
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%gep = getelementptr inbounds i32, ptr %src, i32 %iv
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%l = load i32, ptr %gep
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%c = icmp eq i32 %l, 0
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br i1 %c, label %loop.latch, label %return
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loop.latch:
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%iv.next = add nuw nsw i32 %iv, 1
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%ec = icmp eq i32 %iv.next, 32
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br i1 %ec, label %return, label %loop.header
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return:
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%res.iv1 = phi i32 [ 32, %loop.latch ], [ %iv, %loop.header ]
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%res.iv2 = phi i32 [ 0, %loop.latch ], [ %iv, %loop.header ]
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%res = add i32 %res.iv1, %res.iv2
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ret i32 %res
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}

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