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[RISCV] Further explain vfmerge.vfm/vmerge.vxm varuat coverage
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-fp.ll

Lines changed: 75 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,69 @@ define <4 x double> @shuffle_vf_v4f64(<4 x double> %x) {
6666
ret <4 x double> %s
6767
}
6868

69+
define <4 x float> @vfmerge_constant_v4f32(<4 x float> %x) {
70+
; CHECK-LABEL: vfmerge_constant_v4f32:
71+
; CHECK: # %bb.0:
72+
; CHECK-NEXT: lui a0, 264704
73+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
74+
; CHECK-NEXT: vmv.v.i v0, 6
75+
; CHECK-NEXT: vmv.v.x v9, a0
76+
; CHECK-NEXT: vrgather.vi v8, v9, 1, v0.t
77+
; CHECK-NEXT: ret
78+
%s = shufflevector <4 x float> %x, <4 x float> <float poison, float 5.0, float poison, float poison>, <4 x i32> <i32 0, i32 5, i32 5, i32 3>
79+
ret <4 x float> %s
80+
}
81+
82+
define <4 x double> @vfmerge_constant_v4f64(<4 x double> %x) {
83+
; CHECK-LABEL: vfmerge_constant_v4f64:
84+
; CHECK: # %bb.0:
85+
; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
86+
; CHECK-NEXT: fld fa5, %lo(.LCPI6_0)(a0)
87+
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
88+
; CHECK-NEXT: vmv.v.i v0, 6
89+
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
90+
; CHECK-NEXT: vfmv.v.f v10, fa5
91+
; CHECK-NEXT: vrgather.vi v8, v10, 1, v0.t
92+
; CHECK-NEXT: ret
93+
%s = shufflevector <4 x double> %x, <4 x double> <double poison, double 5.0, double poison, double poison>, <4 x i32> <i32 0, i32 5, i32 5, i32 3>
94+
ret <4 x double> %s
95+
}
96+
97+
define <8 x float> @vmerge_vxm(<8 x float> %v, float %s) {
98+
; CHECK-LABEL: vmerge_vxm:
99+
; CHECK: # %bb.0:
100+
; CHECK-NEXT: li a0, 25
101+
; CHECK-NEXT: vsetivli zero, 8, e32, m1, tu, ma
102+
; CHECK-NEXT: vfmv.s.f v8, fa0
103+
; CHECK-NEXT: vmv.s.x v0, a0
104+
; CHECK-NEXT: vmv2r.v v10, v8
105+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
106+
; CHECK-NEXT: vrgather.vi v10, v8, 0, v0.t
107+
; CHECK-NEXT: vmv.v.v v8, v10
108+
; CHECK-NEXT: ret
109+
%ins = insertelement <8 x float> %v, float %s, i32 0
110+
%shuf = shufflevector <8 x float> %ins, <8 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 0, i32 0, i32 5, i32 6, i32 7>
111+
ret <8 x float> %shuf
112+
}
113+
114+
define <8 x float> @vmerge_vxm2(<8 x float> %v, float %s) {
115+
; CHECK-LABEL: vmerge_vxm2:
116+
; CHECK: # %bb.0:
117+
; CHECK-NEXT: vsetivli zero, 1, e32, m4, tu, ma
118+
; CHECK-NEXT: vmv1r.v v12, v8
119+
; CHECK-NEXT: vmv2r.v v10, v8
120+
; CHECK-NEXT: li a0, 25
121+
; CHECK-NEXT: vfmv.s.f v12, fa0
122+
; CHECK-NEXT: vmv.s.x v0, a0
123+
; CHECK-NEXT: vmv1r.v v10, v12
124+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
125+
; CHECK-NEXT: vrgather.vi v8, v10, 0, v0.t
126+
; CHECK-NEXT: ret
127+
%ins = insertelement <8 x float> %v, float %s, i32 0
128+
%shuf = shufflevector <8 x float> %v, <8 x float> %ins, <8 x i32> <i32 8, i32 1, i32 2, i32 8, i32 8, i32 5, i32 6, i32 7>
129+
ret <8 x float> %shuf
130+
}
131+
69132
define <4 x double> @vrgather_permute_shuffle_vu_v4f64(<4 x double> %x) {
70133
; CHECK-LABEL: vrgather_permute_shuffle_vu_v4f64:
71134
; CHECK: # %bb.0:
@@ -111,8 +174,8 @@ define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) {
111174
; CHECK: # %bb.0:
112175
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
113176
; CHECK-NEXT: vmv.v.i v0, 8
114-
; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
115-
; CHECK-NEXT: fld fa5, %lo(.LCPI8_0)(a0)
177+
; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
178+
; CHECK-NEXT: fld fa5, %lo(.LCPI12_0)(a0)
116179
; CHECK-NEXT: vmv2r.v v10, v8
117180
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
118181
; CHECK-NEXT: vslideup.vi v10, v8, 2, v0.t
@@ -131,8 +194,8 @@ define <4 x double> @vrgather_shuffle_vx_v4f64(<4 x double> %x) {
131194
; CHECK: # %bb.0:
132195
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
133196
; CHECK-NEXT: vmv.v.i v0, 2
134-
; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
135-
; CHECK-NEXT: fld fa5, %lo(.LCPI9_0)(a0)
197+
; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
198+
; CHECK-NEXT: fld fa5, %lo(.LCPI13_0)(a0)
136199
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
137200
; CHECK-NEXT: vslidedown.vi v8, v8, 2, v0.t
138201
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
@@ -378,8 +441,8 @@ define <4 x half> @vrgather_shuffle_vx_v4f16_load(ptr %p) {
378441
define <16 x float> @shuffle_disjoint_lanes(<16 x float> %v, <16 x float> %w) {
379442
; CHECK-LABEL: shuffle_disjoint_lanes:
380443
; CHECK: # %bb.0:
381-
; CHECK-NEXT: lui a0, %hi(.LCPI30_0)
382-
; CHECK-NEXT: addi a0, a0, %lo(.LCPI30_0)
444+
; CHECK-NEXT: lui a0, %hi(.LCPI34_0)
445+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI34_0)
383446
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
384447
; CHECK-NEXT: vle8.v v18, (a0)
385448
; CHECK-NEXT: lui a0, 11
@@ -398,8 +461,8 @@ define <16 x float> @shuffle_disjoint_lanes(<16 x float> %v, <16 x float> %w) {
398461
define <16 x float> @shuffle_disjoint_lanes_one_identity(<16 x float> %v, <16 x float> %w) {
399462
; CHECK-LABEL: shuffle_disjoint_lanes_one_identity:
400463
; CHECK: # %bb.0:
401-
; CHECK-NEXT: lui a0, %hi(.LCPI31_0)
402-
; CHECK-NEXT: addi a0, a0, %lo(.LCPI31_0)
464+
; CHECK-NEXT: lui a0, %hi(.LCPI35_0)
465+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI35_0)
403466
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
404467
; CHECK-NEXT: vle16.v v16, (a0)
405468
; CHECK-NEXT: li a0, -272
@@ -413,8 +476,8 @@ define <16 x float> @shuffle_disjoint_lanes_one_identity(<16 x float> %v, <16 x
413476
define <16 x float> @shuffle_disjoint_lanes_one_broadcast(<16 x float> %v, <16 x float> %w) {
414477
; CHECK-LABEL: shuffle_disjoint_lanes_one_broadcast:
415478
; CHECK: # %bb.0:
416-
; CHECK-NEXT: lui a0, %hi(.LCPI32_0)
417-
; CHECK-NEXT: addi a0, a0, %lo(.LCPI32_0)
479+
; CHECK-NEXT: lui a0, %hi(.LCPI36_0)
480+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI36_0)
418481
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
419482
; CHECK-NEXT: vle16.v v20, (a0)
420483
; CHECK-NEXT: lui a0, 15
@@ -431,8 +494,8 @@ define <16 x float> @shuffle_disjoint_lanes_one_broadcast(<16 x float> %v, <16 x
431494
define <16 x float> @shuffle_disjoint_lanes_one_splat(float %v, <16 x float> %w) {
432495
; CHECK-LABEL: shuffle_disjoint_lanes_one_splat:
433496
; CHECK: # %bb.0:
434-
; CHECK-NEXT: lui a0, %hi(.LCPI33_0)
435-
; CHECK-NEXT: addi a0, a0, %lo(.LCPI33_0)
497+
; CHECK-NEXT: lui a0, %hi(.LCPI37_0)
498+
; CHECK-NEXT: addi a0, a0, %lo(.LCPI37_0)
436499
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
437500
; CHECK-NEXT: vle16.v v16, (a0)
438501
; CHECK-NEXT: lui a0, 15

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1477,3 +1477,17 @@ define <8 x i8> @vmerge_vxm2(<8 x i8> %v, i8 %s) {
14771477
ret <8 x i8> %shuf
14781478
}
14791479

1480+
define <8 x i8> @vmerge_vxm3(<8 x i8> %v, i8 %s) {
1481+
; CHECK-LABEL: vmerge_vxm3:
1482+
; CHECK: # %bb.0:
1483+
; CHECK-NEXT: li a1, 25
1484+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
1485+
; CHECK-NEXT: vmv.s.x v0, a1
1486+
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
1487+
; CHECK-NEXT: ret
1488+
%ins = insertelement <8 x i8> %v, i8 %s, i32 0
1489+
%splat = shufflevector <8 x i8> %ins, <8 x i8> poison, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
1490+
%shuf = shufflevector <8 x i8> %v, <8 x i8> %splat, <8 x i32> <i32 8, i32 1, i32 2, i32 8, i32 8, i32 5, i32 6, i32 7>
1491+
ret <8 x i8> %shuf
1492+
}
1493+

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