Revert "AMDGPU: Treat WMMA XDL ops as TRANS in S_DELAY_ALU insertion for gfx1250 (llvm#149208)"

This reverts commit b52cf75.

Author: ranapratap55

llvm/lib/Target/AMDGPU/AMDGPUInsertDelayAlu.cpp

@@ -25,7 +25,6 @@ namespace {
 
 class AMDGPUInsertDelayAlu {
 public:
-  const GCNSubtarget *ST;
   const SIInstrInfo *SII;
   const TargetRegisterInfo *TRI;
 
@@ -66,16 +65,13 @@ class AMDGPUInsertDelayAlu {
   // Types of delay that can be encoded in an s_delay_alu instruction.
   enum DelayType { VALU, TRANS, SALU, OTHER };
 
-  // Get the delay type for a MachineInstr.
-  DelayType getDelayType(const MachineInstr &MI) {
-    if (SIInstrInfo::isTRANS(MI))
+  // Get the delay type for an instruction with the specified TSFlags.
+  static DelayType getDelayType(uint64_t TSFlags) {
+    if (TSFlags & SIInstrFlags::TRANS)
       return TRANS;
-    // WMMA XDL ops are treated the same as TRANS.
-    if (AMDGPU::isGFX1250(*ST) && SII->isXDLWMMA(MI))
-      return TRANS;
-    if (SIInstrInfo::isVALU(MI))
+    if (TSFlags & SIInstrFlags::VALU)
       return VALU;
-    if (SIInstrInfo::isSALU(MI))
+    if (TSFlags & SIInstrFlags::SALU)
       return SALU;
     return OTHER;
   }
@@ -372,7 +368,7 @@ class AMDGPUInsertDelayAlu {
         continue;
       }
 
-      DelayType Type = getDelayType(MI);
+      DelayType Type = getDelayType(MI.getDesc().TSFlags);
 
       if (instructionWaitsForSGPRWrites(MI)) {
         auto It = State.find(LastSGPRFromVALU);
@@ -460,12 +456,12 @@ class AMDGPUInsertDelayAlu {
     LLVM_DEBUG(dbgs() << "AMDGPUInsertDelayAlu running on " << MF.getName()
                       << "\n");
 
-    ST = &MF.getSubtarget<GCNSubtarget>();
-    if (!ST->hasDelayAlu())
+    const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
+    if (!ST.hasDelayAlu())
       return false;
 
-    SII = ST->getInstrInfo();
-    TRI = ST->getRegisterInfo();
+    SII = ST.getInstrInfo();
+    TRI = ST.getRegisterInfo();
     SchedModel = &SII->getSchedModel();
 
     // Calculate the delay state for each basic block, iterating until we reach

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -10594,23 +10594,10 @@ bool SIInstrInfo::isGlobalMemoryObject(const MachineInstr *MI) const {
   return TargetInstrInfo::isGlobalMemoryObject(MI);
 }
 
-bool SIInstrInfo::isXDLWMMA(const MachineInstr &MI) const {
-  if (!isWMMA(MI) && !isSWMMAC(MI))
-    return false;
-
-  if (AMDGPU::isGFX1250(ST))
-    return AMDGPU::getWMMAIsXDL(MI.getOpcode());
-
-  return true;
-}
-
 bool SIInstrInfo::isXDL(const MachineInstr &MI) const {
   unsigned Opcode = MI.getOpcode();
 
-  if (AMDGPU::isGFX12Plus(ST))
-    return isDOT(MI) || isXDLWMMA(MI);
-
-  if (!isMAI(MI) || isDGEMM(Opcode) ||
+  if (!SIInstrInfo::isMAI(MI) || isDGEMM(Opcode) ||
       Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_e64 ||
       Opcode == AMDGPU::V_ACCVGPR_READ_B32_e64)
     return false;

llvm/lib/Target/AMDGPU/SIInstrInfo.h

@@ -883,8 +883,6 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
     return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
   }
 
-  bool isXDLWMMA(const MachineInstr &MI) const;
-
   bool isXDL(const MachineInstr &MI) const;
 
   static bool isDGEMM(unsigned Opcode) { return AMDGPU::getMAIIsDGEMM(Opcode); }

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

@@ -296,7 +296,6 @@ unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion) {
 #define GET_MIMGOffsetMappingTable_IMPL
 #define GET_MIMGG16MappingTable_IMPL
 #define GET_MAIInstInfoTable_IMPL
-#define GET_WMMAInstInfoTable_IMPL
 #include "AMDGPUGenSearchableTables.inc"
 
 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
@@ -569,11 +568,6 @@ bool getMAIIsGFX940XDL(unsigned Opc) {
   return Info && Info->is_gfx940_xdl;
 }
 
-bool getWMMAIsXDL(unsigned Opc) {
-  const WMMAInstInfo *Info = getWMMAInstInfoHelper(Opc);
-  return Info ? Info->is_wmma_xdl : false;
-}
-
 uint8_t mfmaScaleF8F6F4FormatToNumRegs(unsigned EncodingVal) {
   switch (EncodingVal) {
   case MFMAScaleFormats::FP6_E2M3:

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

@@ -119,11 +119,6 @@ struct True16D16Info {
   unsigned LoOp;
 };
 
-struct WMMAInstInfo {
-  uint16_t Opcode;
-  bool is_wmma_xdl;
-};
-
 #define GET_MIMGBaseOpcode_DECL
 #define GET_MIMGDim_DECL
 #define GET_MIMGEncoding_DECL
@@ -134,7 +129,6 @@ struct WMMAInstInfo {
 #define GET_isMFMA_F8F6F4Table_DECL
 #define GET_isCvtScaleF32_F32F16ToF8F4Table_DECL
 #define GET_True16D16Table_DECL
-#define GET_WMMAInstInfoTable_DECL
 #include "AMDGPUGenSearchableTables.inc"
 
 namespace IsaInfo {
@@ -599,9 +593,6 @@ bool getMAIIsDGEMM(unsigned Opc);
 LLVM_READONLY
 bool getMAIIsGFX940XDL(unsigned Opc);
 
-LLVM_READONLY
-bool getWMMAIsXDL(unsigned Opc);
-
 // Get an equivalent BitOp3 for a binary logical \p Opc.
 // \returns BitOp3 modifier for the logical operation or zero.
 // Used in VOPD3 conversion.